JPS57131144A - Clock reproducing circuit - Google Patents

Abstract

PURPOSE:To obtain a reproducing clock whose S/N ratio is high, by a timing derived from an averaging section for providing a correct timing, by providing 2 averaging sections of a clock timing information, in a digital communication system of multiple access system. CONSTITUTION:A clock signal of an oscillator 3 is divided by a frequency divider 4, outputs a reference signal (g) to a phase transition circuit 10, and also outputs phase difference signals (e), (f) showing a different phase difference each other to said signal (g). When a variation timing of a clock component of a receiving signal (a) is detected by a variation detecting circuit 6 and is inputted to a phase difference averaging circuit as a signal (b), the signals (e), (f) are sampled by this timing, its mean value is outputted as a mean phase difference (h), an averaging section deciding circuit 7 counts the number of samples, and indicates by the signal (h) which signal of (e) or (f) shows a correct phase difference. A storing circuit 9 stores and outputs the mean phase difference under the control of a controlling circuit 11, the phase transition circuit 10 shifts phase of the reference signal (g) by its output (i), and outputs a reproducing clock synchronizing with the clock of the receiving signal.