JPS57117239A - Forming method for polycrystal silicon pattern - Google Patents

Forming method for polycrystal silicon pattern

Info

Publication number
JPS57117239A
JPS57117239A JP298881A JP298881A JPS57117239A JP S57117239 A JPS57117239 A JP S57117239A JP 298881 A JP298881 A JP 298881A JP 298881 A JP298881 A JP 298881A JP S57117239 A JPS57117239 A JP S57117239A
Authority
JP
Japan
Prior art keywords
layer
polycrystal silicon
high concentration
injected
predetermined section
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP298881A
Other languages
Japanese (ja)
Inventor
Shigeru Komatsu
Michio Nakamura
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Tokyo Shibaura Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp, Tokyo Shibaura Electric Co Ltd filed Critical Toshiba Corp
Priority to JP298881A priority Critical patent/JPS57117239A/en
Priority to US06/332,973 priority patent/US4438556A/en
Priority to EP81306155A priority patent/EP0056530B1/en
Priority to DE8181306155T priority patent/DE3167348D1/en
Publication of JPS57117239A publication Critical patent/JPS57117239A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Drying Of Semiconductors (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

PURPOSE:To form the polycrystal silicon pattern with high accuracy without using a mask by selectively injecting the impurity ions of high concentration to the pattern forming predetermined section of a polycrystal silicon layer and plasma-etching unnecessary sections. CONSTITUTION:The impurity ions of high concentration are injected selectively to the pattern forming predetermined section of the polycrystal silicon layer 12. In this case, the layer 12 except the pattern forming predetermined section is coated with a protective film 13 against ion injection, and the ions of high concentration are injected to the whole surface while using the film 13 as a mask. The speed of etching of the layer 12 through plasma etching differs according to the conditions of the layer 12 at that time. This bases a fact that conditions etched are extremely peculiar in the layer 12 into which the impurity ions of high concentration are injected.
JP298881A 1981-01-12 1981-01-12 Forming method for polycrystal silicon pattern Pending JPS57117239A (en)

Priority Applications (4)

Application Number Priority Date Filing Date Title
JP298881A JPS57117239A (en) 1981-01-12 1981-01-12 Forming method for polycrystal silicon pattern
US06/332,973 US4438556A (en) 1981-01-12 1981-12-21 Method of forming doped polycrystalline silicon pattern by selective implantation and plasma etching of undoped regions
EP81306155A EP0056530B1 (en) 1981-01-12 1981-12-24 Process of forming a polycrystalline silicon pattern
DE8181306155T DE3167348D1 (en) 1981-01-12 1981-12-24 Process of forming a polycrystalline silicon pattern

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP298881A JPS57117239A (en) 1981-01-12 1981-01-12 Forming method for polycrystal silicon pattern

Publications (1)

Publication Number Publication Date
JPS57117239A true JPS57117239A (en) 1982-07-21

Family

ID=11544748

Family Applications (1)

Application Number Title Priority Date Filing Date
JP298881A Pending JPS57117239A (en) 1981-01-12 1981-01-12 Forming method for polycrystal silicon pattern

Country Status (1)

Country Link
JP (1) JPS57117239A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS60245228A (en) * 1984-05-21 1985-12-05 Nec Corp Pattern forming method of polysilicon
JPH05129318A (en) * 1991-09-30 1993-05-25 Samsung Electron Co Ltd Manufacture of bipolar transistor

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5650514A (en) * 1979-10-01 1981-05-07 Mitsubishi Electric Corp Formation of fine pattern

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5650514A (en) * 1979-10-01 1981-05-07 Mitsubishi Electric Corp Formation of fine pattern

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS60245228A (en) * 1984-05-21 1985-12-05 Nec Corp Pattern forming method of polysilicon
JPH05129318A (en) * 1991-09-30 1993-05-25 Samsung Electron Co Ltd Manufacture of bipolar transistor

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