JPS55113327A - Introduction of impurity to semiconductor surface - Google Patents

Introduction of impurity to semiconductor surface

Info

Publication number
JPS55113327A
JPS55113327A JP1981579A JP1981579A JPS55113327A JP S55113327 A JPS55113327 A JP S55113327A JP 1981579 A JP1981579 A JP 1981579A JP 1981579 A JP1981579 A JP 1981579A JP S55113327 A JPS55113327 A JP S55113327A
Authority
JP
Japan
Prior art keywords
slope
gate
substrate
ions
parallel
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP1981579A
Other languages
Japanese (ja)
Inventor
Ryoichi Fukuyama
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP1981579A priority Critical patent/JPS55113327A/en
Publication of JPS55113327A publication Critical patent/JPS55113327A/en
Pending legal-status Critical Current

Links

Abstract

PURPOSE: To obtain a gate of a minute length by injecting ions into the slope of one side of a V groove on a substrate and in parallel to it and selectively injecting an impurity into the surface of the substrate including the slope of the groove on the other side.
CONSTITUTION: An n+ layers 3, 4 are formed on surface (100) of p-type Si substrate 1, and V-shaped groove 5 with slope surface (111) of a minute width is formed on the gate part, and this is covered with gate oxide electrode 6. Next, when n layers 7, 8 are formed by injecting P ions from the direction of A into the substrate in parallel to the slope, no ions are injected into part 9. Next, poly-Si 10 is evaporated from the direction of B in parallel to the slope. Next, by photo-etching poly-Si 10, gate electrode 10 is formed. Subsequently, this is covered with PSG11, and by selectively opening it, Al 12 is evaporated, and thereby electrodes S, D, G are formed. By this structure, a gate of a minute length can be formed with extremely high precision without regard to mask errors and the like.
COPYRIGHT: (C)1980,JPO&Japio
JP1981579A 1979-02-23 1979-02-23 Introduction of impurity to semiconductor surface Pending JPS55113327A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP1981579A JPS55113327A (en) 1979-02-23 1979-02-23 Introduction of impurity to semiconductor surface

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1981579A JPS55113327A (en) 1979-02-23 1979-02-23 Introduction of impurity to semiconductor surface

Publications (1)

Publication Number Publication Date
JPS55113327A true JPS55113327A (en) 1980-09-01

Family

ID=12009813

Family Applications (1)

Application Number Title Priority Date Filing Date
JP1981579A Pending JPS55113327A (en) 1979-02-23 1979-02-23 Introduction of impurity to semiconductor surface

Country Status (1)

Country Link
JP (1) JPS55113327A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS58184767A (en) * 1982-04-23 1983-10-28 Clarion Co Ltd V-type mosfet with load
JP2007013080A (en) * 2005-06-30 2007-01-18 Hynix Semiconductor Inc Method for manufacturing semiconductor device

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS58184767A (en) * 1982-04-23 1983-10-28 Clarion Co Ltd V-type mosfet with load
JP2007013080A (en) * 2005-06-30 2007-01-18 Hynix Semiconductor Inc Method for manufacturing semiconductor device

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