JPS57113133A - Numeric input equipment - Google Patents

Abstract

PURPOSE:To perform input operation by a down key with display 0 in a short time by resetting the most significant digit number to a counter and then by performing successive counting-down operation by operating the down key while the smallest value is set to the counter. CONSTITUTION:The outputs of AND circuits A1 and A2 are inputted to a decimal up-down counter CNT; when the counter counts up to contents 9, an H- level signal E is outputted and when counting down to a 0, an H-level signal E' is outputted. When a down key K2 is pressed with, for example, count display 0, an FF2 is reset by the output B' of a key debounce circuit, so its set output F' is at a level L and an NAND gate output G' is at a level H. Consequently, a pulse C passes through the AND gate A2 and a signal D' permits the counter to count down, so the counter changes from 0 to 9 and, when the key is further depressed, stops at 0, thus performing input operation by the down key with display 0 in a short time.