JPS57140055A - Cmi coding circuit - Google Patents

Cmi coding circuit

Info

Publication number
JPS57140055A
JPS57140055A JP2419881A JP2419881A JPS57140055A JP S57140055 A JPS57140055 A JP S57140055A JP 2419881 A JP2419881 A JP 2419881A JP 2419881 A JP2419881 A JP 2419881A JP S57140055 A JPS57140055 A JP S57140055A
Authority
JP
Japan
Prior art keywords
output
clock
terminal
input
input signal
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP2419881A
Other languages
Japanese (ja)
Inventor
Yoshitaka Kato
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp, Nippon Electric Co Ltd filed Critical NEC Corp
Priority to JP2419881A priority Critical patent/JPS57140055A/en
Publication of JPS57140055A publication Critical patent/JPS57140055A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L25/00—Baseband systems
    • H04L25/38—Synchronous or start-stop systems, e.g. for Baudot code
    • H04L25/40—Transmitting circuits; Receiving circuits
    • H04L25/49—Transmitting circuits; Receiving circuits using code conversion at the transmitter; using predistortion; using insertion of idle bits for obtaining a desired frequency spectrum; using three or more amplitude levels ; Baseband coding techniques specific to data transmission systems
    • H04L25/4906—Transmitting circuits; Receiving circuits using code conversion at the transmitter; using predistortion; using insertion of idle bits for obtaining a desired frequency spectrum; using three or more amplitude levels ; Baseband coding techniques specific to data transmission systems using binary codes
    • H04L25/4908—Transmitting circuits; Receiving circuits using code conversion at the transmitter; using predistortion; using insertion of idle bits for obtaining a desired frequency spectrum; using three or more amplitude levels ; Baseband coding techniques specific to data transmission systems using binary codes using mBnB codes
    • H04L25/491—Transmitting circuits; Receiving circuits using code conversion at the transmitter; using predistortion; using insertion of idle bits for obtaining a desired frequency spectrum; using three or more amplitude levels ; Baseband coding techniques specific to data transmission systems using binary codes using mBnB codes using 1B2B codes
    • H04L25/4912—Transmitting circuits; Receiving circuits using code conversion at the transmitter; using predistortion; using insertion of idle bits for obtaining a desired frequency spectrum; using three or more amplitude levels ; Baseband coding techniques specific to data transmission systems using binary codes using mBnB codes using 1B2B codes using CMI or 2-HDB-3 code

Landscapes

  • Physics & Mathematics (AREA)
  • Spectroscopy & Molecular Physics (AREA)
  • Engineering & Computer Science (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Dc Digital Transmission (AREA)

Abstract

PURPOSE:To avoid the delay in a half clock width and to decrease the circuit scale, by inputting an input signal of NRZ code to a selection signal input of a selection circuit, in a CMI coding circuit having a violation generating function. CONSTITUTION:An input signal (i) of NRZ code at a terminal 11 and a clock input signal (j) at a terminal 12 are inputted to an NAND gate 13, and the output becomes a clock input of a D-FF14. When an input signal (h) at a terminal 10 goes to 1, the counting of a mode 2 stopps, and the output (m) of an exclusive OR gate 15 acts like the same operation as the stopping of count at a leading of a clock (k). When the output (m) of the gate 15 and the clock signal (j) at the terminal 12 are inputted to input sides A, B, an output (n) of the selection circuit 16 becomes a CMI coding output having the violation generating function of the CMI rule.
JP2419881A 1981-02-23 1981-02-23 Cmi coding circuit Pending JPS57140055A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2419881A JPS57140055A (en) 1981-02-23 1981-02-23 Cmi coding circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2419881A JPS57140055A (en) 1981-02-23 1981-02-23 Cmi coding circuit

Publications (1)

Publication Number Publication Date
JPS57140055A true JPS57140055A (en) 1982-08-30

Family

ID=12131621

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2419881A Pending JPS57140055A (en) 1981-02-23 1981-02-23 Cmi coding circuit

Country Status (1)

Country Link
JP (1) JPS57140055A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS632427A (en) * 1986-06-21 1988-01-07 Nec Corp Code conversion circuit

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS632427A (en) * 1986-06-21 1988-01-07 Nec Corp Code conversion circuit

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