JPS57100681A - Data processing system - Google Patents

Data processing system

Info

Publication number
JPS57100681A
JPS57100681A JP55176409A JP17640980A JPS57100681A JP S57100681 A JPS57100681 A JP S57100681A JP 55176409 A JP55176409 A JP 55176409A JP 17640980 A JP17640980 A JP 17640980A JP S57100681 A JPS57100681 A JP S57100681A
Authority
JP
Japan
Prior art keywords
erasure
control parts
buffer storage
processing
buffer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP55176409A
Other languages
Japanese (ja)
Inventor
Kiyoshi Oguri
Hideki Fukuoka
Akira Nakajima
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Nippon Telegraph and Telephone Corp
Original Assignee
Nippon Telegraph and Telephone Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Nippon Telegraph and Telephone Corp filed Critical Nippon Telegraph and Telephone Corp
Priority to JP55176409A priority Critical patent/JPS57100681A/en
Publication of JPS57100681A publication Critical patent/JPS57100681A/en
Pending legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F15/00—Digital computers in general; Data processing equipment in general
    • G06F15/16—Combinations of two or more digital computers each having at least an arithmetic unit, a program unit and a register, e.g. for a simultaneous processing of several programs
    • G06F15/163—Interprocessor communication
    • G06F15/167—Interprocessor communication using a common memory, e.g. mailbox

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Theoretical Computer Science (AREA)
  • Software Systems (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Memory System Of A Hierarchy Structure (AREA)

Abstract

PURPOSE:To enable high-speed processing without interrupting normal processing and to improve the performance of a buffer storage device, by informing hardware of a part, where central processors do not use information in common, through software. CONSTITUTION:Central processors 1 and 2 are provided with display elements 8 and 9 for buffer-storage invalidating processing requests, and erasure request control parts 12 and 13 are provided with the function of judging the invalidating processing request. Then, when display elements 8 and 9 show ''1''s, the con- trol parts 12 and 13 detect those, and write address from write control parts 10 and 11 are regarded as erasure request addresses. Buffer storage erasure control parts 6 and 7 compare the erasure request addresses with an address stored in an address array A and, only when they are coincident, make corresponding blocks of buffer storage devices 4 and 5 insignificant.
JP55176409A 1980-12-13 1980-12-13 Data processing system Pending JPS57100681A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP55176409A JPS57100681A (en) 1980-12-13 1980-12-13 Data processing system

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP55176409A JPS57100681A (en) 1980-12-13 1980-12-13 Data processing system

Publications (1)

Publication Number Publication Date
JPS57100681A true JPS57100681A (en) 1982-06-22

Family

ID=16013166

Family Applications (1)

Application Number Title Priority Date Filing Date
JP55176409A Pending JPS57100681A (en) 1980-12-13 1980-12-13 Data processing system

Country Status (1)

Country Link
JP (1) JPS57100681A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS60138653A (en) * 1983-12-27 1985-07-23 Hitachi Ltd Hierarchical memory control system

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS60138653A (en) * 1983-12-27 1985-07-23 Hitachi Ltd Hierarchical memory control system
JPH0576060B2 (en) * 1983-12-27 1993-10-21 Hitachi Ltd

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