JPS5491028A - Memory control system of multiprocessor system - Google Patents

Memory control system of multiprocessor system

Info

Publication number
JPS5491028A
JPS5491028A JP15796477A JP15796477A JPS5491028A JP S5491028 A JPS5491028 A JP S5491028A JP 15796477 A JP15796477 A JP 15796477A JP 15796477 A JP15796477 A JP 15796477A JP S5491028 A JPS5491028 A JP S5491028A
Authority
JP
Japan
Prior art keywords
data
main memory
units
memory
cpus
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP15796477A
Other languages
Japanese (ja)
Inventor
Masanobu Inoue
Kunio Ono
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp, Nippon Electric Co Ltd filed Critical NEC Corp
Priority to JP15796477A priority Critical patent/JPS5491028A/en
Publication of JPS5491028A publication Critical patent/JPS5491028A/en
Pending legal-status Critical Current

Links

Abstract

PURPOSE: To enable simple constitution to attain memory control by adding hard ware which functions to make data on a cash memory in a multiprocessor system agree with that on a main memory unit.
CONSTITUTION: This system is equipped with main memory units 7 and 8 stored with data on a block unit and CPUs 1 and 2 which possess cash memory part 11 stored with data equivalent to blocks on the block unit. Further, this is provided with input-output transfer controllers 3 and 4 which transfer data from an input device to other units including CPUs 1 and 2 and data from any other unit to an output device, and main memory controllers 5 and 6 which transfer as one group of data write data, write address and requesting-device discriminating information to main memory units 7 and 8 answering to a write request from either CPUS 1 and 2 or units 3 and 4. Then, a block on memory part 11 indicated by the write address from main memory units 7 and 8 is made ineffective.
COPYRIGHT: (C)1979,JPO&Japio
JP15796477A 1977-12-28 1977-12-28 Memory control system of multiprocessor system Pending JPS5491028A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP15796477A JPS5491028A (en) 1977-12-28 1977-12-28 Memory control system of multiprocessor system

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP15796477A JPS5491028A (en) 1977-12-28 1977-12-28 Memory control system of multiprocessor system

Publications (1)

Publication Number Publication Date
JPS5491028A true JPS5491028A (en) 1979-07-19

Family

ID=15661286

Family Applications (1)

Application Number Title Priority Date Filing Date
JP15796477A Pending JPS5491028A (en) 1977-12-28 1977-12-28 Memory control system of multiprocessor system

Country Status (1)

Country Link
JP (1) JPS5491028A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS58500226A (en) * 1981-03-24 1983-02-10 バロ−ス・コ−ポレ−ション Apparatus and method for maintaining cache memory integrity in a shared memory environment
JPS6476345A (en) * 1987-09-18 1989-03-22 Fujitsu Ltd Disk cache control system

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS58500226A (en) * 1981-03-24 1983-02-10 バロ−ス・コ−ポレ−ション Apparatus and method for maintaining cache memory integrity in a shared memory environment
JPS6476345A (en) * 1987-09-18 1989-03-22 Fujitsu Ltd Disk cache control system

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