JPS5712469A - Buffer memory control system - Google Patents
Buffer memory control systemInfo
- Publication number
- JPS5712469A JPS5712469A JP8371380A JP8371380A JPS5712469A JP S5712469 A JPS5712469 A JP S5712469A JP 8371380 A JP8371380 A JP 8371380A JP 8371380 A JP8371380 A JP 8371380A JP S5712469 A JPS5712469 A JP S5712469A
- Authority
- JP
- Japan
- Prior art keywords
- buffer memory
- memory
- desired data
- control system
- memory control
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
- G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
Abstract
PURPOSE:To eliminate cancel process of a buffer memory to the write given from a processor and then increase the performance of the constitution using a number of processors, by properly using plural buffer memories following to the control information. CONSTITUTION:A read request given from a processor 11 (or 12-14) is sent to a buffer memory 15 or a buffer memory 20 within a control part 21, and the data is read when a desired data exists in the memory 15 or 20 to be stored in a register 22. If no desired data exists on the memory, the read request is sent to a main storage device 19. Then the desired data is transferred to the memory 15 or 20 from the device 19, and at the same time the desired data is stored in the register 22.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP8371380A JPS5712469A (en) | 1980-06-20 | 1980-06-20 | Buffer memory control system |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP8371380A JPS5712469A (en) | 1980-06-20 | 1980-06-20 | Buffer memory control system |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS5712469A true JPS5712469A (en) | 1982-01-22 |
Family
ID=13810137
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP8371380A Pending JPS5712469A (en) | 1980-06-20 | 1980-06-20 | Buffer memory control system |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS5712469A (en) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH01107165A (en) * | 1987-10-20 | 1989-04-25 | Iwatsu Electric Co Ltd | Free running circuit |
Citations (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS533217A (en) * | 1976-06-28 | 1978-01-12 | Fuji Photo Film Co Ltd | Image formation |
-
1980
- 1980-06-20 JP JP8371380A patent/JPS5712469A/en active Pending
Patent Citations (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS533217A (en) * | 1976-06-28 | 1978-01-12 | Fuji Photo Film Co Ltd | Image formation |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH01107165A (en) * | 1987-10-20 | 1989-04-25 | Iwatsu Electric Co Ltd | Free running circuit |
JPH0547071B2 (en) * | 1987-10-20 | 1993-07-15 | Iwatsu Electric Co Ltd |
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