JPS5597655A - Memory access system - Google Patents

Memory access system

Info

Publication number
JPS5597655A
JPS5597655A JP433279A JP433279A JPS5597655A JP S5597655 A JPS5597655 A JP S5597655A JP 433279 A JP433279 A JP 433279A JP 433279 A JP433279 A JP 433279A JP S5597655 A JPS5597655 A JP S5597655A
Authority
JP
Japan
Prior art keywords
memory
request
control part
information
access
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP433279A
Other languages
Japanese (ja)
Inventor
Akira Kaneko
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mitsubishi Electric Corp
Original Assignee
Mitsubishi Electric Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsubishi Electric Corp filed Critical Mitsubishi Electric Corp
Priority to JP433279A priority Critical patent/JPS5597655A/en
Publication of JPS5597655A publication Critical patent/JPS5597655A/en
Pending legal-status Critical Current

Links

Abstract

PURPOSE: To secure the memory access time equivalent to the cycle time of the memory by providing more than two sets of information buffers for writing and reading to the memory plus more than two sets of reading and writing request control parts to the CPU respectively.
CONSTITUTION: When the request is generated within CPU2 to memory 1, request control part 4 is set to send the request to the memory. Memory 1 memorizes the request given from CPU2 into information buffer 8 and then starts the access of the memory unit through memory unit access information selection control part 10. In case the request to the next memory is occurred in CPU2 during that time, request control part 5 is set. And request selection control part 6 switches the request control to memory 1 to part 5. And memory 1 memorizes the request information into information buffer 9, and at the same time memory busy display control part 13 is set. On the other hand, when the access is over via buffer 8, the data is set to data buffer 12 to secure the request enable state.
COPYRIGHT: (C)1980,JPO&Japio
JP433279A 1979-01-18 1979-01-18 Memory access system Pending JPS5597655A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP433279A JPS5597655A (en) 1979-01-18 1979-01-18 Memory access system

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP433279A JPS5597655A (en) 1979-01-18 1979-01-18 Memory access system

Publications (1)

Publication Number Publication Date
JPS5597655A true JPS5597655A (en) 1980-07-25

Family

ID=11581487

Family Applications (1)

Application Number Title Priority Date Filing Date
JP433279A Pending JPS5597655A (en) 1979-01-18 1979-01-18 Memory access system

Country Status (1)

Country Link
JP (1) JPS5597655A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5812185A (en) * 1981-07-15 1983-01-24 Nec Corp Semiconductor storage device

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5812185A (en) * 1981-07-15 1983-01-24 Nec Corp Semiconductor storage device
JPS628870B2 (en) * 1981-07-15 1987-02-25 Nippon Electric Co

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