JPS55157037A - Processing system for multiplication and division - Google Patents

Processing system for multiplication and division

Info

Publication number
JPS55157037A
JPS55157037A JP6365979A JP6365979A JPS55157037A JP S55157037 A JPS55157037 A JP S55157037A JP 6365979 A JP6365979 A JP 6365979A JP 6365979 A JP6365979 A JP 6365979A JP S55157037 A JPS55157037 A JP S55157037A
Authority
JP
Japan
Prior art keywords
output
upper rank
produced
input
multiplication
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP6365979A
Other languages
Japanese (ja)
Inventor
Osamu Maeda
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP6365979A priority Critical patent/JPS55157037A/en
Publication of JPS55157037A publication Critical patent/JPS55157037A/en
Pending legal-status Critical Current

Links

Abstract

PURPOSE: To speed up the data processing speed, by detecting the number of consecutive zeros at the upper rank bit of data and performing shift operation according to them, for very high speed operation of the multiplication and division of fixed decimal point.
CONSTITUTION: The number of zeros detection section 9 is provided. The detection section 9 detects the number of consecutive zeros in the upper rank bit of the multiplier B, and if the upper rank 6-digit is consecutively 0, an output is produced at the output terminal C3. At least, when in upper rank 4 digits, the output is produced in C2 and in other cases, output is produced in C1. Multiplicands A(a31a30...b2b1 b0) are respectively input to the first and second input registers 1, 2 and multipliers B (b21b20...b2b1b0) are input to the third input register 8. Next, when A-B is calculated, the partial products 3 (a31Wa0)×(b3b2b1b0), (a31Wa0)×(a7 b6b5b4... are individually obtained and they are added 6.
COPYRIGHT: (C)1980,JPO&Japio
JP6365979A 1979-05-23 1979-05-23 Processing system for multiplication and division Pending JPS55157037A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP6365979A JPS55157037A (en) 1979-05-23 1979-05-23 Processing system for multiplication and division

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP6365979A JPS55157037A (en) 1979-05-23 1979-05-23 Processing system for multiplication and division

Publications (1)

Publication Number Publication Date
JPS55157037A true JPS55157037A (en) 1980-12-06

Family

ID=13235687

Family Applications (1)

Application Number Title Priority Date Filing Date
JP6365979A Pending JPS55157037A (en) 1979-05-23 1979-05-23 Processing system for multiplication and division

Country Status (1)

Country Link
JP (1) JPS55157037A (en)

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