JPS567152A - Address stopping system for arithmetic process system - Google Patents

Address stopping system for arithmetic process system

Info

Publication number
JPS567152A
JPS567152A JP8319079A JP8319079A JPS567152A JP S567152 A JPS567152 A JP S567152A JP 8319079 A JP8319079 A JP 8319079A JP 8319079 A JP8319079 A JP 8319079A JP S567152 A JPS567152 A JP S567152A
Authority
JP
Japan
Prior art keywords
address
circuit
stop
order
coincidence
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP8319079A
Other languages
Japanese (ja)
Other versions
JPS595931B2 (en
Inventor
Hiroshi Hashimoto
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Tokyo Shibaura Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp, Tokyo Shibaura Electric Co Ltd filed Critical Toshiba Corp
Priority to JP54083190A priority Critical patent/JPS595931B2/en
Publication of JPS567152A publication Critical patent/JPS567152A/en
Publication of JPS595931B2 publication Critical patent/JPS595931B2/en
Expired legal-status Critical Current

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  • Debugging And Monitoring (AREA)

Abstract

PURPOSE: To ensure the assured execution for the stop order at the designated address, by securing the coincidence of the stop address previously at the external comparator and then changing the order word to make the order prefetch circuit read the order word.
CONSTITUTION: The address delivered from address output circuit 11 is held at address latch circuit 22. The address held at circuit 22 is compared with the address sent from stop address setting circuit 23 and set previously through comparator 21. And in case no coincidence is obtained, the address held at circuit 22 selects memory 25 via address decoder 24. The data sent from selected memory 25 is stored in order prefetch circuit 12 via circuit 11. In case the coincidence is obtained between the addresses sent from circuits 22 and 23 each, the stop order code is delivered from stop order code output circuit 27 to be taken into circuit 12 via circuit 11. At arithmetic part 13, the contents in circuit 12 are processed in sequence, and the stop order is executed at the stop address for stoppage.
COPYRIGHT: (C)1981,JPO&Japio
JP54083190A 1979-06-30 1979-06-30 Address stop method for arithmetic processing system Expired JPS595931B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP54083190A JPS595931B2 (en) 1979-06-30 1979-06-30 Address stop method for arithmetic processing system

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP54083190A JPS595931B2 (en) 1979-06-30 1979-06-30 Address stop method for arithmetic processing system

Publications (2)

Publication Number Publication Date
JPS567152A true JPS567152A (en) 1981-01-24
JPS595931B2 JPS595931B2 (en) 1984-02-08

Family

ID=13795396

Family Applications (1)

Application Number Title Priority Date Filing Date
JP54083190A Expired JPS595931B2 (en) 1979-06-30 1979-06-30 Address stop method for arithmetic processing system

Country Status (1)

Country Link
JP (1) JPS595931B2 (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH04350735A (en) * 1991-05-29 1992-12-04 Nec Corp Microprocessor

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH01161731U (en) * 1988-04-30 1989-11-10

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH04350735A (en) * 1991-05-29 1992-12-04 Nec Corp Microprocessor

Also Published As

Publication number Publication date
JPS595931B2 (en) 1984-02-08

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