JPS54161856A - Starting method of microprocessor - Google Patents

Starting method of microprocessor

Info

Publication number
JPS54161856A
JPS54161856A JP7167278A JP7167278A JPS54161856A JP S54161856 A JPS54161856 A JP S54161856A JP 7167278 A JP7167278 A JP 7167278A JP 7167278 A JP7167278 A JP 7167278A JP S54161856 A JPS54161856 A JP S54161856A
Authority
JP
Japan
Prior art keywords
gate
program
output
starting time
rom
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP7167278A
Other languages
Japanese (ja)
Other versions
JPS5858701B2 (en
Inventor
Toshiro Hirao
Goro Hamano
Katsumi Fujisaki
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Holdings Corp
Original Assignee
Matsushita Electric Industrial Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matsushita Electric Industrial Co Ltd filed Critical Matsushita Electric Industrial Co Ltd
Priority to JP7167278A priority Critical patent/JPS5858701B2/en
Publication of JPS54161856A publication Critical patent/JPS54161856A/en
Publication of JPS5858701B2 publication Critical patent/JPS5858701B2/en
Expired legal-status Critical Current

Links

Abstract

PURPOSE: To continue the program execution in the normal memory space by replacing the addresses between the RAM region containing the memory start address and the ROM region containing the control program of the system at the starting time for execution of the program and then having reload under programing.
CONSTITUTION: Memory space 40 is divided into three RAM's and one ROM regions each of which is selected through address control gates 10W13. The memory region is converted at FF50 and reset with the signals of starting time. The start address of the starting time is 0000 with the selection signals delivered from gate 10 and does not enter RAM40 via AND gate 20 with output Q of FF50. While the output of gate 12 is supplied to ROM via OR gate 30 with output Q- of FF50, and the processor operates based on the program stored. In such constitution, the RAM region can be set regardless of the start address.
COPYRIGHT: (C)1979,JPO&Japio
JP7167278A 1978-06-13 1978-06-13 How to start a microprocessor Expired JPS5858701B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP7167278A JPS5858701B2 (en) 1978-06-13 1978-06-13 How to start a microprocessor

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP7167278A JPS5858701B2 (en) 1978-06-13 1978-06-13 How to start a microprocessor

Publications (2)

Publication Number Publication Date
JPS54161856A true JPS54161856A (en) 1979-12-21
JPS5858701B2 JPS5858701B2 (en) 1983-12-27

Family

ID=13467305

Family Applications (1)

Application Number Title Priority Date Filing Date
JP7167278A Expired JPS5858701B2 (en) 1978-06-13 1978-06-13 How to start a microprocessor

Country Status (1)

Country Link
JP (1) JPS5858701B2 (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6254349A (en) * 1985-09-02 1987-03-10 Nec Corp Address modification system
US7136965B2 (en) 2000-08-07 2006-11-14 Nec Corporation Microcomputer

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6254349A (en) * 1985-09-02 1987-03-10 Nec Corp Address modification system
US7136965B2 (en) 2000-08-07 2006-11-14 Nec Corporation Microcomputer

Also Published As

Publication number Publication date
JPS5858701B2 (en) 1983-12-27

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