JPS5693163A - Buffer access control system - Google Patents

Buffer access control system

Info

Publication number
JPS5693163A
JPS5693163A JP16858479A JP16858479A JPS5693163A JP S5693163 A JPS5693163 A JP S5693163A JP 16858479 A JP16858479 A JP 16858479A JP 16858479 A JP16858479 A JP 16858479A JP S5693163 A JPS5693163 A JP S5693163A
Authority
JP
Japan
Prior art keywords
access
memory
main memory
buffer memory
move
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP16858479A
Other languages
Japanese (ja)
Inventor
Noriyuki Toyoki
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP16858479A priority Critical patent/JPS5693163A/en
Publication of JPS5693163A publication Critical patent/JPS5693163A/en
Pending legal-status Critical Current

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  • Memory System Of A Hierarchy Structure (AREA)

Abstract

PURPOSE: To increase the efficiency of process, by giving a permission only to the fetch access for the access to a buffer memory for the period during which the subject of replacement sent from the main memory has a move-in after the move-in is started.
CONSTITUTION: No request data is given to the buffer memory receiving a swap control along with the main memory from an arithmetic device, and the fetch/ store flags FV and SV are respecting turned to 1 and 0 via the address register 1 and the tag part 3 of the buffer memory. Then the comparator 8 delivers the coincidence output when a coincidence is obtained between a part of the register 1 and the address of the part 3. The AND gate 6 is opened by the coincidence output. Only the fetch access receives a permission of access for the period during which the subject data moves in the memory part 2 of the buffer memory from the main memory. Accordingly, the data is processed without repeating move-in again and after returned to the main memory, thus increasing the efficiency of process.
COPYRIGHT: (C)1981,JPO&Japio
JP16858479A 1979-12-25 1979-12-25 Buffer access control system Pending JPS5693163A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP16858479A JPS5693163A (en) 1979-12-25 1979-12-25 Buffer access control system

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP16858479A JPS5693163A (en) 1979-12-25 1979-12-25 Buffer access control system

Publications (1)

Publication Number Publication Date
JPS5693163A true JPS5693163A (en) 1981-07-28

Family

ID=15870758

Family Applications (1)

Application Number Title Priority Date Filing Date
JP16858479A Pending JPS5693163A (en) 1979-12-25 1979-12-25 Buffer access control system

Country Status (1)

Country Link
JP (1) JPS5693163A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2007096998A1 (en) * 2006-02-24 2007-08-30 Fujitsu Limited Cache memory device and cache memory control method

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2007096998A1 (en) * 2006-02-24 2007-08-30 Fujitsu Limited Cache memory device and cache memory control method

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