JPS5563439A - Instruction control system for direct data bit - Google Patents

Instruction control system for direct data bit

Info

Publication number
JPS5563439A
JPS5563439A JP13713878A JP13713878A JPS5563439A JP S5563439 A JPS5563439 A JP S5563439A JP 13713878 A JP13713878 A JP 13713878A JP 13713878 A JP13713878 A JP 13713878A JP S5563439 A JPS5563439 A JP S5563439A
Authority
JP
Japan
Prior art keywords
instruction
rom
instructions
data
data bit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP13713878A
Other languages
Japanese (ja)
Inventor
Akira Nagano
Kazuaki Urasaki
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Omron Corp
Original Assignee
Omron Tateisi Electronics Co
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Omron Tateisi Electronics Co filed Critical Omron Tateisi Electronics Co
Priority to JP13713878A priority Critical patent/JPS5563439A/en
Publication of JPS5563439A publication Critical patent/JPS5563439A/en
Pending legal-status Critical Current

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Abstract

PURPOSE: To use the decoder with efficiency so that the instructions of two types are incorporated into one instruction to reduce the number of instructions decoded and the resulting instruction can be used for another instruction being decode outputted.
CONSTITUTION: The microcomputer includes the program counter 1, stack register 2, address control section 3, and ROM 4, the instruction read out from ROM is inputted to the latch circuit 3 and it is held for one step. The output is fed to the decoder 6 and various instructions are decoded and outputted. The gate circuits 7W10 selects either one of the direct data bit stored in ROM and the contents of the register 16 and it is derived to the data bus 11 in 4 bits. Further, the logic operation circuit 12 makes logical operation with the contents of the accumulator 13 and the data derived on the data bus 11 and stores the result in the accumulator 13. RAM 14 stores various data.
COPYRIGHT: (C)1980,JPO&Japio
JP13713878A 1978-11-06 1978-11-06 Instruction control system for direct data bit Pending JPS5563439A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP13713878A JPS5563439A (en) 1978-11-06 1978-11-06 Instruction control system for direct data bit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP13713878A JPS5563439A (en) 1978-11-06 1978-11-06 Instruction control system for direct data bit

Publications (1)

Publication Number Publication Date
JPS5563439A true JPS5563439A (en) 1980-05-13

Family

ID=15191701

Family Applications (1)

Application Number Title Priority Date Filing Date
JP13713878A Pending JPS5563439A (en) 1978-11-06 1978-11-06 Instruction control system for direct data bit

Country Status (1)

Country Link
JP (1) JPS5563439A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS61216027A (en) * 1985-02-14 1986-09-25 Fujitsu Ltd Microprogram processing system
JPH0250222A (en) * 1988-08-11 1990-02-20 Nec Corp Operand supplying system

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS61216027A (en) * 1985-02-14 1986-09-25 Fujitsu Ltd Microprogram processing system
JPH0250222A (en) * 1988-08-11 1990-02-20 Nec Corp Operand supplying system

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