JPS5666057A - Formation of electrode of semiconductor element - Google Patents

Formation of electrode of semiconductor element

Info

Publication number
JPS5666057A
JPS5666057A JP14130279A JP14130279A JPS5666057A JP S5666057 A JPS5666057 A JP S5666057A JP 14130279 A JP14130279 A JP 14130279A JP 14130279 A JP14130279 A JP 14130279A JP S5666057 A JPS5666057 A JP S5666057A
Authority
JP
Japan
Prior art keywords
electrode
film
mask
tin
melt
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP14130279A
Other languages
Japanese (ja)
Inventor
Hiroaki Okudaira
Masanori Nakamura
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP14130279A priority Critical patent/JPS5666057A/en
Publication of JPS5666057A publication Critical patent/JPS5666057A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/11—Manufacturing methods
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    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/03—Manufacturing methods
    • H01L2224/0347—Manufacturing methods using a lift-off mask
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    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/03—Manufacturing methods
    • H01L2224/036—Manufacturing methods by patterning a pre-deposited material
    • H01L2224/0361—Physical or chemical etching
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    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/03—Manufacturing methods
    • H01L2224/039—Methods of manufacturing bonding areas involving a specific sequence of method steps
    • H01L2224/03912—Methods of manufacturing bonding areas involving a specific sequence of method steps the bump being used as a mask for patterning the bonding area
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    • H01L2224/03914—Methods of manufacturing bonding areas involving a specific sequence of method steps the bonding area, e.g. under bump metallisation [UBM], being used as a mask for patterning other parts
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    • H01L2224/05572—Disposition the external layer being disposed in a recess of the surface the external layer extending out of an opening
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    • H01L2224/118—Post-treatment of the bump connector
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    • H01L2924/014—Solder alloys

Landscapes

  • Engineering & Computer Science (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Electroplating Methods And Accessories (AREA)

Abstract

PURPOSE:To contrive the miniaturization of semiconductor device by a method wherein a metal film having little wettability against solder is piled on a ground film for electrode, a resin mask is provided to perform plating, the solder is stripped off from the metal film by heating to melt and is collected to the desired electrode part. CONSTITUTION:The ground film 4 of copper is formed on a substrate 3 provided with an Al wiring 1 and a protective film 2. Ti 8 is evaporated and a resist mask 5 is provided to form an opening 9. Ni 10 is plated and a resist mask 5' is newly provided to plate head 11, tin 12. The mask 5' is removed and is heated to melt, and the lead 11, the tin 12 are collected on the Ni 10 forming a spherically protruded electrode 13. The Ti 8 and the copper ground film 4 are selectively removed to complete the electrode. In this constitution, the interval between the electrodes can be reduced by suitably designing a plating pattern 8' and the element can be highly integrated.
JP14130279A 1979-11-02 1979-11-02 Formation of electrode of semiconductor element Pending JPS5666057A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP14130279A JPS5666057A (en) 1979-11-02 1979-11-02 Formation of electrode of semiconductor element

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP14130279A JPS5666057A (en) 1979-11-02 1979-11-02 Formation of electrode of semiconductor element

Publications (1)

Publication Number Publication Date
JPS5666057A true JPS5666057A (en) 1981-06-04

Family

ID=15288718

Family Applications (1)

Application Number Title Priority Date Filing Date
JP14130279A Pending JPS5666057A (en) 1979-11-02 1979-11-02 Formation of electrode of semiconductor element

Country Status (1)

Country Link
JP (1) JPS5666057A (en)

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6054456A (en) * 1983-09-05 1985-03-28 Oki Electric Ind Co Ltd Forming method of bump electrode
US4950623A (en) * 1988-08-02 1990-08-21 Microelectronics Center Of North Carolina Method of building solder bumps
US5289631A (en) * 1992-03-04 1994-03-01 Mcnc Method for testing, burn-in, and/or programming of integrated circuit chips
US5767010A (en) * 1995-03-20 1998-06-16 Mcnc Solder bump fabrication methods and structure including a titanium barrier layer
US6462414B1 (en) * 1999-03-05 2002-10-08 Altera Corporation Integrated circuit package utilizing a conductive structure for interlocking a conductive ball to a ball pad
US7446399B1 (en) 2004-08-04 2008-11-04 Altera Corporation Pad structures to improve board-level reliability of solder-on-pad BGA structures

Cited By (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6054456A (en) * 1983-09-05 1985-03-28 Oki Electric Ind Co Ltd Forming method of bump electrode
US4950623A (en) * 1988-08-02 1990-08-21 Microelectronics Center Of North Carolina Method of building solder bumps
US5289631A (en) * 1992-03-04 1994-03-01 Mcnc Method for testing, burn-in, and/or programming of integrated circuit chips
US5374893A (en) * 1992-03-04 1994-12-20 Mcnc Apparatus for testing, burn-in, and/or programming of integrated circuit chips, and for placing solder bumps thereon
US5381946A (en) * 1992-03-04 1995-01-17 Mcnc Method of forming differing volume solder bumps
US5767010A (en) * 1995-03-20 1998-06-16 Mcnc Solder bump fabrication methods and structure including a titanium barrier layer
US6222279B1 (en) 1995-03-20 2001-04-24 Mcnc Solder bump fabrication methods and structures including a titanium barrier layer
US6462414B1 (en) * 1999-03-05 2002-10-08 Altera Corporation Integrated circuit package utilizing a conductive structure for interlocking a conductive ball to a ball pad
US6929978B2 (en) 1999-03-05 2005-08-16 Altera Corporation Method of fabricating an integrated circuit package utilizing a conductive structure for improving the bond strength between an IC package and a printed circuit board
US7446399B1 (en) 2004-08-04 2008-11-04 Altera Corporation Pad structures to improve board-level reliability of solder-on-pad BGA structures

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