JPS566525A - 2-phase clock pulse generating circuit - Google Patents

2-phase clock pulse generating circuit

Info

Publication number
JPS566525A
JPS566525A JP8135279A JP8135279A JPS566525A JP S566525 A JPS566525 A JP S566525A JP 8135279 A JP8135279 A JP 8135279A JP 8135279 A JP8135279 A JP 8135279A JP S566525 A JPS566525 A JP S566525A
Authority
JP
Japan
Prior art keywords
circuit
output
gate
input
phase clock
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP8135279A
Other languages
Japanese (ja)
Inventor
Tatsuaki Ueno
Kenichi Fukushima
Yutaka Shinagawa
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Renesas Eastern Japan Semiconductor Inc
Original Assignee
Hitachi Tokyo Electronics Co Ltd
Hitachi Ltd
Hitachi Ome Electronic Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Tokyo Electronics Co Ltd, Hitachi Ltd, Hitachi Ome Electronic Co Ltd filed Critical Hitachi Tokyo Electronics Co Ltd
Priority to JP8135279A priority Critical patent/JPS566525A/en
Publication of JPS566525A publication Critical patent/JPS566525A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
    • H03K5/15—Arrangements in which pulses are delivered at different times at several outputs, i.e. pulse distributors
    • H03K5/151—Arrangements in which pulses are delivered at different times at several outputs, i.e. pulse distributors with two complementary outputs

Landscapes

  • Physics & Mathematics (AREA)
  • Nonlinear Science (AREA)
  • Manipulation Of Pulses (AREA)

Abstract

PURPOSE:To secure the compensation for the signal delay at the clock signal line in the 2-phase clock pulse generating circuit consisting of the latch circuit, by producing the feedback signal via the delay circuit. CONSTITUTION:The 1-phase clock signal CP is applied to inverting circuit IN1 to produce signal CP'. Then clock signal CP is applied to the 1st input of NOR gate circuit G1, and at the same time clock signal CP' is supplied to the 1st input of NOR gate G2 each. The output of NOR gate circuit G1 is turned into output CP''' via the output buffer circuit consisting of the inverted push-pull circuit; and the output of NOR gate circuit G2 is turned into output CP'' via the output buffer circuit. Then output CP''' is fed back to the 2nd input of NOR gate circuit G2 via delay circuit DL2; and output CP'' is fed back to the 2nd input of NOR gate circuit G1 via delay circuit DL1 respectively.
JP8135279A 1979-06-29 1979-06-29 2-phase clock pulse generating circuit Pending JPS566525A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP8135279A JPS566525A (en) 1979-06-29 1979-06-29 2-phase clock pulse generating circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP8135279A JPS566525A (en) 1979-06-29 1979-06-29 2-phase clock pulse generating circuit

Publications (1)

Publication Number Publication Date
JPS566525A true JPS566525A (en) 1981-01-23

Family

ID=13743963

Family Applications (1)

Application Number Title Priority Date Filing Date
JP8135279A Pending JPS566525A (en) 1979-06-29 1979-06-29 2-phase clock pulse generating circuit

Country Status (1)

Country Link
JP (1) JPS566525A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH01311718A (en) * 1988-06-10 1989-12-15 Nec Ic Microcomput Syst Ltd Clock driver circuit
US9378789B2 (en) 2014-09-26 2016-06-28 Qualcomm Incorporated Voltage level shifted self-clocked write assistance

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5218630B1 (en) * 1966-03-21 1977-05-23

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5218630B1 (en) * 1966-03-21 1977-05-23

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH01311718A (en) * 1988-06-10 1989-12-15 Nec Ic Microcomput Syst Ltd Clock driver circuit
US9378789B2 (en) 2014-09-26 2016-06-28 Qualcomm Incorporated Voltage level shifted self-clocked write assistance

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