JPS54142058A - Logic circuit - Google Patents

Logic circuit

Info

Publication number
JPS54142058A
JPS54142058A JP5086278A JP5086278A JPS54142058A JP S54142058 A JPS54142058 A JP S54142058A JP 5086278 A JP5086278 A JP 5086278A JP 5086278 A JP5086278 A JP 5086278A JP S54142058 A JPS54142058 A JP S54142058A
Authority
JP
Japan
Prior art keywords
signal
rise
current capacity
begins
phi1
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP5086278A
Other languages
Japanese (ja)
Other versions
JPS641976B2 (en
Inventor
Akira Osami
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp, Nippon Electric Co Ltd filed Critical NEC Corp
Priority to JP5086278A priority Critical patent/JPS54142058A/en
Publication of JPS54142058A publication Critical patent/JPS54142058A/en
Publication of JPS641976B2 publication Critical patent/JPS641976B2/ja
Granted legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
    • H03K19/08—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices
    • H03K19/094—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices using field-effect transistors
    • H03K19/096—Synchronous circuits, i.e. using clock signals

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Computing Systems (AREA)
  • General Engineering & Computer Science (AREA)
  • Mathematical Physics (AREA)
  • Logic Circuits (AREA)

Abstract

PURPOSE:To facilitate the control of the delay time for the activation timing by connecting the MOSFET's of different current capacity in series between power sources and then applying the output signal and the signal sent from the input to the gate of MOSFET each. CONSTITUTION:When basic input clock inversion phiTTL of RAM shifts from H to L level and then enters the active period, MOSFETQ3 and Q6 become inconductive and the potential of node 2 begins to rise via MOSFETQ2. As a result, node 5 of MOSFETQ8 and Q9 connected in series between the power sources becomes L level, and MOSFETQ7 becomes inconductive with Q5 turned conductive. And activation timing signal phi1 begins to rise. When the rising of signal phi1 is over, signal P begins to rise. Signal P is then applied to the gate of FETQ8. The current capacity of FETQ9 is set larger than FETQ8, and at the same time the current capacity of FETQ7 is set larger enough than Q5. As a result, the rise of signal phi1 can be accelerated. The rise time of signal phi1 is adjusted through setting of the current capacity of Q8 and Q9, thus obtaining the necessary address setup time.
JP5086278A 1978-04-27 1978-04-27 Logic circuit Granted JPS54142058A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP5086278A JPS54142058A (en) 1978-04-27 1978-04-27 Logic circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP5086278A JPS54142058A (en) 1978-04-27 1978-04-27 Logic circuit

Publications (2)

Publication Number Publication Date
JPS54142058A true JPS54142058A (en) 1979-11-05
JPS641976B2 JPS641976B2 (en) 1989-01-13

Family

ID=12870522

Family Applications (1)

Application Number Title Priority Date Filing Date
JP5086278A Granted JPS54142058A (en) 1978-04-27 1978-04-27 Logic circuit

Country Status (1)

Country Link
JP (1) JPS54142058A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5711533A (en) * 1980-06-25 1982-01-21 Mitsubishi Electric Corp Output circuit for mos integrated circuit

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5135272A (en) * 1974-09-20 1976-03-25 Hitachi Ltd

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5135272A (en) * 1974-09-20 1976-03-25 Hitachi Ltd

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5711533A (en) * 1980-06-25 1982-01-21 Mitsubishi Electric Corp Output circuit for mos integrated circuit
JPH0324098B2 (en) * 1980-06-25 1991-04-02 Mitsubishi Electric Corp

Also Published As

Publication number Publication date
JPS641976B2 (en) 1989-01-13

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