JPS5534518A - Lsi parameter setting system - Google Patents

Lsi parameter setting system

Info

Publication number
JPS5534518A
JPS5534518A JP10630978A JP10630978A JPS5534518A JP S5534518 A JPS5534518 A JP S5534518A JP 10630978 A JP10630978 A JP 10630978A JP 10630978 A JP10630978 A JP 10630978A JP S5534518 A JPS5534518 A JP S5534518A
Authority
JP
Japan
Prior art keywords
parameter setting
terminal
setting
output
parameter
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP10630978A
Other languages
Japanese (ja)
Inventor
Hiroshi Yasukawa
Nobuhiko Owada
Tadakatsu Kimura
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Nippon Telegraph and Telephone Corp
Original Assignee
Nippon Telegraph and Telephone Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Nippon Telegraph and Telephone Corp filed Critical Nippon Telegraph and Telephone Corp
Priority to JP10630978A priority Critical patent/JPS5534518A/en
Publication of JPS5534518A publication Critical patent/JPS5534518A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
    • H03K19/173—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components

Abstract

PURPOSE:To minimize the number of the setting terminals in case the parameter is set up at the IC or SI by securing the setting or definition for more than two parameters via one unit of the parameter setting terminal. CONSTITUTION:Parameter setting signals H and L plus signal 2T featuring the H and L alternating in period T are supplied through parameter setting terminal S. The clock pulse of period T is applied to terminal T from clock pulse generator 2, and the parameter setting signal is latched by latch circuit 1 with the fixed period timing. Input X1 and output X2 of circuit 1 are supplied to AND gate 3 and OR gate 4, and the output S1 and S2 deliver three sets of output signals H/H, L/L and H/L through terminal S based on the table and in accordance with input H, L and 2T each.
JP10630978A 1978-09-01 1978-09-01 Lsi parameter setting system Pending JPS5534518A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP10630978A JPS5534518A (en) 1978-09-01 1978-09-01 Lsi parameter setting system

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP10630978A JPS5534518A (en) 1978-09-01 1978-09-01 Lsi parameter setting system

Publications (1)

Publication Number Publication Date
JPS5534518A true JPS5534518A (en) 1980-03-11

Family

ID=14430383

Family Applications (1)

Application Number Title Priority Date Filing Date
JP10630978A Pending JPS5534518A (en) 1978-09-01 1978-09-01 Lsi parameter setting system

Country Status (1)

Country Link
JP (1) JPS5534518A (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS619017A (en) * 1984-05-31 1986-01-16 ゼネラル・エレクトリック・カンパニイ Programmable buffer
JPS6349962A (en) * 1986-08-20 1988-03-02 Matsushita Electric Ind Co Ltd Device for designating lsi operation mode
US5986468A (en) * 1991-03-06 1999-11-16 Quicklogic Corporation Programmable application specific integrated circuit and logic cell therefor

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS619017A (en) * 1984-05-31 1986-01-16 ゼネラル・エレクトリック・カンパニイ Programmable buffer
JPH0554732B2 (en) * 1984-05-31 1993-08-13 Gen Electric
JPS6349962A (en) * 1986-08-20 1988-03-02 Matsushita Electric Ind Co Ltd Device for designating lsi operation mode
US5986468A (en) * 1991-03-06 1999-11-16 Quicklogic Corporation Programmable application specific integrated circuit and logic cell therefor
US6078191A (en) * 1991-03-06 2000-06-20 Quicklogic Corporation Programmable application specific integrated circuit and logic cell

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