JPS5662463A - Dummy bit addition system to facsimile video signal - Google Patents

Dummy bit addition system to facsimile video signal

Info

Publication number
JPS5662463A
JPS5662463A JP13893179A JP13893179A JPS5662463A JP S5662463 A JPS5662463 A JP S5662463A JP 13893179 A JP13893179 A JP 13893179A JP 13893179 A JP13893179 A JP 13893179A JP S5662463 A JPS5662463 A JP S5662463A
Authority
JP
Japan
Prior art keywords
video signal
memory
coder
register
transfer request
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP13893179A
Other languages
Japanese (ja)
Other versions
JPS6346627B2 (en
Inventor
Kenichi Hanabe
Toshio Suhara
Kenzo Nakabashi
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Nippon Telegraph and Telephone Corp
Original Assignee
Fujitsu Ltd
Nippon Telegraph and Telephone Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd, Nippon Telegraph and Telephone Corp filed Critical Fujitsu Ltd
Priority to JP13893179A priority Critical patent/JPS5662463A/en
Publication of JPS5662463A publication Critical patent/JPS5662463A/en
Publication of JPS6346627B2 publication Critical patent/JPS6346627B2/ja
Granted legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N1/00—Scanning, transmission or reproduction of documents or the like, e.g. facsimile transmission; Details thereof
    • H04N1/41—Bandwidth or redundancy reduction

Landscapes

  • Engineering & Computer Science (AREA)
  • Multimedia (AREA)
  • Signal Processing (AREA)
  • Facsimiles In General (AREA)
  • Storing Facsimile Image Data (AREA)
  • Communication Control (AREA)

Abstract

PURPOSE:To enable the connection of video signal without incurring the increase in the hardware, by providing a logic gate at the transmission interface to the storage section of buffer memory, and by switching the transmission of effective video signal and that of read skip information with the switching of the logic gate. CONSTITUTION:Serial video signal and clock are input to a coder 10 via video signal line 14 and a clock line 15 to store the video signal to a given unit, and transfer request is made from the coder 10 to a control section 13, the write-in address is transmitted from the control section 13 to the memory 9, and parallel data is written in the memory 9 from the coder 10. When this amount of write- in reaches a given amount, transfer request is made via a transfer request line 19 to a common control device 8. Further, the effective data from the memory 9 is transferred to a buffer register 11 and fed to a storage section 6 via the register 11. When the effective data is finished for the transfer from the memory 9 to the register 11, the control signal to an AND circuit 12 is made zero, and all the data transmitted after that are made zero, the clear circuit for the memory circuit is made unnecessary and the connection of video signal can effectively be made.
JP13893179A 1979-10-27 1979-10-27 Dummy bit addition system to facsimile video signal Granted JPS5662463A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP13893179A JPS5662463A (en) 1979-10-27 1979-10-27 Dummy bit addition system to facsimile video signal

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP13893179A JPS5662463A (en) 1979-10-27 1979-10-27 Dummy bit addition system to facsimile video signal

Publications (2)

Publication Number Publication Date
JPS5662463A true JPS5662463A (en) 1981-05-28
JPS6346627B2 JPS6346627B2 (en) 1988-09-16

Family

ID=15233481

Family Applications (1)

Application Number Title Priority Date Filing Date
JP13893179A Granted JPS5662463A (en) 1979-10-27 1979-10-27 Dummy bit addition system to facsimile video signal

Country Status (1)

Country Link
JP (1) JPS5662463A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS58116842A (en) * 1981-12-29 1983-07-12 Matsushita Electric Ind Co Ltd Data processing method of multiple address repeating device
JPS63127672A (en) * 1986-11-18 1988-05-31 Matsushita Electric Ind Co Ltd Picture signal processing unit

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS58116842A (en) * 1981-12-29 1983-07-12 Matsushita Electric Ind Co Ltd Data processing method of multiple address repeating device
JPS63127672A (en) * 1986-11-18 1988-05-31 Matsushita Electric Ind Co Ltd Picture signal processing unit

Also Published As

Publication number Publication date
JPS6346627B2 (en) 1988-09-16

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