JPS5635432A - Manufacturing of mos integrated circuit device - Google Patents

Manufacturing of mos integrated circuit device

Info

Publication number
JPS5635432A
JPS5635432A JP11033779A JP11033779A JPS5635432A JP S5635432 A JPS5635432 A JP S5635432A JP 11033779 A JP11033779 A JP 11033779A JP 11033779 A JP11033779 A JP 11033779A JP S5635432 A JPS5635432 A JP S5635432A
Authority
JP
Japan
Prior art keywords
substrate
film
electrode
diffused
impurities
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP11033779A
Other languages
Japanese (ja)
Inventor
Hiroshi Nozawa
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Tokyo Shibaura Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp, Tokyo Shibaura Electric Co Ltd filed Critical Toshiba Corp
Priority to JP11033779A priority Critical patent/JPS5635432A/en
Publication of JPS5635432A publication Critical patent/JPS5635432A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76Making of isolation regions between components
    • H01L21/762Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/76202Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using a local oxidation of silicon, e.g. LOCOS, SWAMI, SILO

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Element Separation (AREA)

Abstract

PURPOSE:To avoid generation of defective articles due to hot electron by applying an insulating film on an MOS IC forming a predetermined element region, diffusing P impurities on the film to perform gettering, and diffusing As impurities reducing the lifetime of the carrier on the back surface of the substrate. CONSTITUTION:Thick field SiO2 films 2 are formed on the peripheral edge parts of a P type Si substrate 1, and this gate SiO2 film 3 is applied on the surface of the substrate 1 encircled by the above film 2. A gate electrode 4 composed of polycrystal Si is formed at the central part of the SiO2 film 3. Then, by using the electrode 4 as a mask. As is diffused in the substrate 1 at both sides of the electrode 4 to form an N type source and drain regions 5 and 6. The full surfaces of these regions 5 and 6 are coated with an insulating film and P is diffused thereon to perform gettering. Then, a high impurities concentration layer on the surface layer is eliminated. Thereafter, on the back surface of the substrate 1, an As diffused layer 8 is formed to shorten the lifetime of the substrate 1, and a window is formed in the remaining film 7, while an Al internal wiring 9 being fitted to the electrode 4.
JP11033779A 1979-08-31 1979-08-31 Manufacturing of mos integrated circuit device Pending JPS5635432A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP11033779A JPS5635432A (en) 1979-08-31 1979-08-31 Manufacturing of mos integrated circuit device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP11033779A JPS5635432A (en) 1979-08-31 1979-08-31 Manufacturing of mos integrated circuit device

Publications (1)

Publication Number Publication Date
JPS5635432A true JPS5635432A (en) 1981-04-08

Family

ID=14533188

Family Applications (1)

Application Number Title Priority Date Filing Date
JP11033779A Pending JPS5635432A (en) 1979-08-31 1979-08-31 Manufacturing of mos integrated circuit device

Country Status (1)

Country Link
JP (1) JPS5635432A (en)

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS58209965A (en) * 1982-06-01 1983-12-07 Teruaki Shimazu Nutritious food product
JPS6049777A (en) * 1983-08-30 1985-03-19 Koichiro Kawabata Nutritive food and its preparation
JPS6125461A (en) * 1984-07-16 1986-02-04 Yoshihiro Ishibashi Tablet containing component of lotus root
JPH0198463A (en) * 1987-10-09 1989-04-17 Masaichi Kamiya Tangle-containing rice bran food

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS58209965A (en) * 1982-06-01 1983-12-07 Teruaki Shimazu Nutritious food product
JPS6049777A (en) * 1983-08-30 1985-03-19 Koichiro Kawabata Nutritive food and its preparation
JPS6125461A (en) * 1984-07-16 1986-02-04 Yoshihiro Ishibashi Tablet containing component of lotus root
JPH0198463A (en) * 1987-10-09 1989-04-17 Masaichi Kamiya Tangle-containing rice bran food

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