JPS5633823A - Preparation of semiconductor device - Google Patents

Preparation of semiconductor device

Info

Publication number
JPS5633823A
JPS5633823A JP11005379A JP11005379A JPS5633823A JP S5633823 A JPS5633823 A JP S5633823A JP 11005379 A JP11005379 A JP 11005379A JP 11005379 A JP11005379 A JP 11005379A JP S5633823 A JPS5633823 A JP S5633823A
Authority
JP
Japan
Prior art keywords
oxide film
drain
source
concave parts
electrodes
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP11005379A
Other languages
Japanese (ja)
Inventor
Yoshimasa Ishii
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Tokyo Shibaura Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp, Tokyo Shibaura Electric Co Ltd filed Critical Toshiba Corp
Priority to JP11005379A priority Critical patent/JPS5633823A/en
Publication of JPS5633823A publication Critical patent/JPS5633823A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268

Abstract

PURPOSE:To enable obtaining low contact resistance connection even if contact holes are small by making concave parts on the conductive regions formed on a semiconductor substrate and connecting electrodes to these concave parts. CONSTITUTION:When forming source and drain electrodes in an MOS integrated circuit, n<+> conductive regions 14 and 15 are formed by coating a silicon oxide film 12 selectively on a p type silicon substrate 11 and diffusing impurities from openings 13. Next, the silicon oxide film 12 is etched to a required thickness and then a field oxide film 16 is formed on the source 14 and the drain 15. Further, contact holes 18 are formed in the field oxide film 16, and by applying anisotropic etching, concave parts 19 are formed on the source 14 and the drain 15. Then by depositing Al from the surface, source and drain take-out electrodes 20, 21 and a gate electrode 22 are formed.
JP11005379A 1979-08-29 1979-08-29 Preparation of semiconductor device Pending JPS5633823A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP11005379A JPS5633823A (en) 1979-08-29 1979-08-29 Preparation of semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP11005379A JPS5633823A (en) 1979-08-29 1979-08-29 Preparation of semiconductor device

Publications (1)

Publication Number Publication Date
JPS5633823A true JPS5633823A (en) 1981-04-04

Family

ID=14525892

Family Applications (1)

Application Number Title Priority Date Filing Date
JP11005379A Pending JPS5633823A (en) 1979-08-29 1979-08-29 Preparation of semiconductor device

Country Status (1)

Country Link
JP (1) JPS5633823A (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS59117115A (en) * 1982-12-08 1984-07-06 インタ−ナシヨナル・レクチフアイヤ−・コ−ポレ−シヨン Method of producing semiconductor device
US4914050A (en) * 1984-09-03 1990-04-03 Kabushiki Kaisha Toshiba Semiconductor device and manufacturing method thereof
US5084418A (en) * 1988-12-27 1992-01-28 Texas Instruments Incorporated Method of making an array device with buried interconnects

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS59117115A (en) * 1982-12-08 1984-07-06 インタ−ナシヨナル・レクチフアイヤ−・コ−ポレ−シヨン Method of producing semiconductor device
US4914050A (en) * 1984-09-03 1990-04-03 Kabushiki Kaisha Toshiba Semiconductor device and manufacturing method thereof
US5084418A (en) * 1988-12-27 1992-01-28 Texas Instruments Incorporated Method of making an array device with buried interconnects

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