JPS5533235A - Microprogram control system - Google Patents
Microprogram control systemInfo
- Publication number
- JPS5533235A JPS5533235A JP10602578A JP10602578A JPS5533235A JP S5533235 A JPS5533235 A JP S5533235A JP 10602578 A JP10602578 A JP 10602578A JP 10602578 A JP10602578 A JP 10602578A JP S5533235 A JPS5533235 A JP S5533235A
- Authority
- JP
- Japan
- Prior art keywords
- register
- skip
- address
- clock
- pipeline register
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Landscapes
- Advance Control (AREA)
- Executing Machine-Instructions (AREA)
Abstract
PURPOSE: To reduce the number of microsteps under pipelined microprogram control by making a skip while inhibiting the supply of a clock pulse to a pipeline register with a flip-flop set.
CONSTITUTION: For example, a skip instruction stored at an A+1 address, the contents of an A address is stored in pipeline register 3, and logical operation circuit 4 performs the process. The next, clock sets the skip instruction to pipeline register 3 and also sets a flags, etc., from logical operation circuit 4 to status register 6. A decision on whether the contents of register 6 and pipeline register 3 meet the condition, and skip flip-flop 10 is set so as to inhibit the supply of the clock to pipeline register 3. However, the clock to ROS address register 2 is effective, so that a skip over the A+2 address will be made without outputting its contents.
COPYRIGHT: (C)1980,JPO&Japio
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP10602578A JPS5533235A (en) | 1978-08-30 | 1978-08-30 | Microprogram control system |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP10602578A JPS5533235A (en) | 1978-08-30 | 1978-08-30 | Microprogram control system |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS5533235A true JPS5533235A (en) | 1980-03-08 |
Family
ID=14423091
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP10602578A Pending JPS5533235A (en) | 1978-08-30 | 1978-08-30 | Microprogram control system |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS5533235A (en) |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP0037935A2 (en) * | 1980-03-31 | 1981-10-21 | Northern Telecom Limited | Sequence control circuit for a computer |
| JPS62282331A (en) * | 1986-05-31 | 1987-12-08 | Canon Inc | Arithmetic processing unit |
| US5771376A (en) * | 1995-10-06 | 1998-06-23 | Nippondenso Co., Ltd | Pipeline arithmetic and logic system with clock control function for selectively supplying clock to a given unit |
| JP2008530693A (en) * | 2005-02-10 | 2008-08-07 | クゥアルコム・インコーポレイテッド | Conditional instruction execution via an emissary instruction for condition evaluation |
-
1978
- 1978-08-30 JP JP10602578A patent/JPS5533235A/en active Pending
Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP0037935A2 (en) * | 1980-03-31 | 1981-10-21 | Northern Telecom Limited | Sequence control circuit for a computer |
| JPS56152052A (en) * | 1980-03-31 | 1981-11-25 | Northern Telecom Ltd | Sequencial control circuit for computer |
| JPS62282331A (en) * | 1986-05-31 | 1987-12-08 | Canon Inc | Arithmetic processing unit |
| US5771376A (en) * | 1995-10-06 | 1998-06-23 | Nippondenso Co., Ltd | Pipeline arithmetic and logic system with clock control function for selectively supplying clock to a given unit |
| JP2008530693A (en) * | 2005-02-10 | 2008-08-07 | クゥアルコム・インコーポレイテッド | Conditional instruction execution via an emissary instruction for condition evaluation |
| JP4903720B2 (en) * | 2005-02-10 | 2012-03-28 | クゥアルコム・インコーポレイテッド | Conditional instruction execution via an emissary instruction for condition evaluation |
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