JPS5714259A - Vertical synchronizing signal separation circuit - Google Patents

Abstract

PURPOSE:To make stable the circuit, by obtaining a vertical synchronizing signal separated from a pulse generating circuit delaying a television composite synchronizing signal for a given time limit and a latch circuit sampling and storing this as a clock signal. CONSTITUTION:A composite synchronizing signal (a) is inputted to a differentiator 4 to form an output waveform (b), and it is also supplied to a data input D of a D type FF5. A monostable circuit 6 constitutes a pulse generating circuit together with the device 4, and when it is triggered, a signal 6a having 1/4H pulse width as shown in the waveform (c) and this is taken as the clock signal and applied to a timing input T of the FF5. The FF5 operates as a latch circuit which samples and stores the logic level of the composite synchronizing signal at the trailing of the signal 6a and outputs a synchronizing signal (d) as a result. Thus, a stable vertical synchronizing signal can be obtained with good accuracy without being affected with temperature change and noise.