JPS56159750A - Bus control system - Google Patents

Bus control system

Info

Publication number
JPS56159750A
JPS56159750A JP6363380A JP6363380A JPS56159750A JP S56159750 A JPS56159750 A JP S56159750A JP 6363380 A JP6363380 A JP 6363380A JP 6363380 A JP6363380 A JP 6363380A JP S56159750 A JPS56159750 A JP S56159750A
Authority
JP
Japan
Prior art keywords
bus
storage device
modules
area
refer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP6363380A
Other languages
Japanese (ja)
Inventor
Hiroaki Inada
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Tokyo Shibaura Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp, Tokyo Shibaura Electric Co Ltd filed Critical Toshiba Corp
Priority to JP6363380A priority Critical patent/JPS56159750A/en
Publication of JPS56159750A publication Critical patent/JPS56159750A/en
Pending legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/36—Handling requests for interconnection or transfer for access to common bus or bus system

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Storage Device Security (AREA)
  • Bus Control (AREA)

Abstract

PURPOSE:To reduce a load on a CPU by permitting respective modules connected to a bus to refer to a flag area freely and by inhibiting modules except a module which refers to the area first, to refer said area until the processing of the module ends. CONSTITUTION:Logic is added to a CPU2, an input-output controller 3 and a file controller 4 connected to a main storage device 1 via a bus 5. In normal operation, a bus request signal BUSREQ, when sent by the input-output controller 3 to refer to a common area in the main storage device 1, is judged to be a signal BUS OK from an adjacent module and after it is confirmed that the bus 5 is nor used by other modules, an F.F.13 is set to output a signal BUSY, thereby occupying the bus. When the system bus 5 is to be used continuously >=2 times, a burst request BREQ is generated to set the F.F.13 for a BUSBUSY, so that while the main storage device 1 is referred to, the contents of the common area of the storage device 1 is protected without being referred to by other modules.
JP6363380A 1980-05-14 1980-05-14 Bus control system Pending JPS56159750A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP6363380A JPS56159750A (en) 1980-05-14 1980-05-14 Bus control system

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP6363380A JPS56159750A (en) 1980-05-14 1980-05-14 Bus control system

Publications (1)

Publication Number Publication Date
JPS56159750A true JPS56159750A (en) 1981-12-09

Family

ID=13234938

Family Applications (1)

Application Number Title Priority Date Filing Date
JP6363380A Pending JPS56159750A (en) 1980-05-14 1980-05-14 Bus control system

Country Status (1)

Country Link
JP (1) JPS56159750A (en)

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6095666A (en) * 1983-10-28 1985-05-29 Fujitsu Ltd Interface controlling method
JPS63168758A (en) * 1987-01-07 1988-07-12 Fujitsu Ltd Multi-bus control system
JPH0623969B2 (en) * 1987-05-01 1994-03-30 ディジタル イクイプメント コーポレーション Apparatus and method for allowing a node to gain access to a bus
JPH0782476B2 (en) * 1987-05-01 1995-09-06 ディジタル イクイプメント コーポレーション A system that controls access to the reservation bus by multiple nodes

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6095666A (en) * 1983-10-28 1985-05-29 Fujitsu Ltd Interface controlling method
JPS63168758A (en) * 1987-01-07 1988-07-12 Fujitsu Ltd Multi-bus control system
JPH0623969B2 (en) * 1987-05-01 1994-03-30 ディジタル イクイプメント コーポレーション Apparatus and method for allowing a node to gain access to a bus
JPH0782476B2 (en) * 1987-05-01 1995-09-06 ディジタル イクイプメント コーポレーション A system that controls access to the reservation bus by multiple nodes

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