JPS5759222A - Dma data transfer system - Google Patents

Dma data transfer system

Info

Publication number
JPS5759222A
JPS5759222A JP13435780A JP13435780A JPS5759222A JP S5759222 A JPS5759222 A JP S5759222A JP 13435780 A JP13435780 A JP 13435780A JP 13435780 A JP13435780 A JP 13435780A JP S5759222 A JPS5759222 A JP S5759222A
Authority
JP
Japan
Prior art keywords
cpu1
data transfer
dma
main memory
permission flag
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP13435780A
Other languages
Japanese (ja)
Inventor
Hideya Sato
Seiichi Yasumoto
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP13435780A priority Critical patent/JPS5759222A/en
Publication of JPS5759222A publication Critical patent/JPS5759222A/en
Pending legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/20—Handling requests for interconnection or transfer for access to input/output bus
    • G06F13/28—Handling requests for interconnection or transfer for access to input/output bus using burst mode transfer, e.g. direct memory access DMA, cycle steal
    • G06F13/285—Halt processor DMA

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Bus Control (AREA)

Abstract

PURPOSE:To reduce a load on a CPU by decreasing the frequency of interruption to the CPU due to DMA transfer with regard to an input and output equipment whose amount of data transferred once is small and where data are generated at random. CONSTITUTION:The main memory 3 of a CPU1 is enabled to be referred to freely and directly from an input-output controller IOC2. In an optional address of the main memory 3, a control information storage area 4 for DMA data transfer is provided and a DMA data transfer permission flag is set there; and the permission flag for control information is read at a constant period, and according to the condition establishment of the DMA data transfer permission flag, asynchronous data transfer from the IOC2 to the main memory 3 of the CPU1 is achieved without any start command from the CPU1. Therefore, the frequency of interruption to the CPU1 due to the DMA transfer is decreased to reduce a load on the CPU1.
JP13435780A 1980-09-29 1980-09-29 Dma data transfer system Pending JPS5759222A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP13435780A JPS5759222A (en) 1980-09-29 1980-09-29 Dma data transfer system

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP13435780A JPS5759222A (en) 1980-09-29 1980-09-29 Dma data transfer system

Publications (1)

Publication Number Publication Date
JPS5759222A true JPS5759222A (en) 1982-04-09

Family

ID=15126473

Family Applications (1)

Application Number Title Priority Date Filing Date
JP13435780A Pending JPS5759222A (en) 1980-09-29 1980-09-29 Dma data transfer system

Country Status (1)

Country Link
JP (1) JPS5759222A (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6228861A (en) * 1985-07-30 1987-02-06 Mita Ind Co Ltd Data transfer system
JPS6258356A (en) * 1985-05-24 1987-03-14 Omron Tateisi Electronics Co Dma controller
US5240816A (en) * 1990-06-18 1993-08-31 Asahi Glass Company Ltd. Method of producing a screen for printing a heating line pattern and a method of forming a heating line pattern on a glass plate

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6258356A (en) * 1985-05-24 1987-03-14 Omron Tateisi Electronics Co Dma controller
JPS6228861A (en) * 1985-07-30 1987-02-06 Mita Ind Co Ltd Data transfer system
US5240816A (en) * 1990-06-18 1993-08-31 Asahi Glass Company Ltd. Method of producing a screen for printing a heating line pattern and a method of forming a heating line pattern on a glass plate

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