JPS6478353A - Data transfer method for microcomputer - Google Patents
Data transfer method for microcomputerInfo
- Publication number
- JPS6478353A JPS6478353A JP15328788A JP15328788A JPS6478353A JP S6478353 A JPS6478353 A JP S6478353A JP 15328788 A JP15328788 A JP 15328788A JP 15328788 A JP15328788 A JP 15328788A JP S6478353 A JPS6478353 A JP S6478353A
- Authority
- JP
- Japan
- Prior art keywords
- cpu
- data
- transfer
- dma control
- carried out
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/14—Handling requests for interconnection or transfer
- G06F13/20—Handling requests for interconnection or transfer for access to input/output bus
- G06F13/28—Handling requests for interconnection or transfer for access to input/output bus using burst mode transfer, e.g. direct memory access DMA, cycle steal
- G06F13/285—Halt processor DMA
Landscapes
- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Bus Control (AREA)
Abstract
PURPOSE:To transfer a large quantity of data in a short time without deteriorating the instantaneous response properties of a CPU, by transferring data in a cycle still mode during CPU operation and then separating the CPU from a bus as long as the CPU is not active to transfer data by continuous DMA control. CONSTITUTION:Data is transferred in a cycle still mode as long as a CPU 12 is active when a request is received for transfer of data to be carried out between a memory 13 and an input and/or output device 17 based on the DMA control. While the CPU 12 is separated from a bus 15 in case the CPU 12 is inactive and the data is transferred by the continuous DMA control of a circuit 14. Thus it is possible to improve the efficiency of DMA transfer with the instantaneous response properties secured for the data transfer carried out by the CPU 12 and that carried out by the DMA control.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP63153287A JPH0693235B2 (en) | 1987-06-25 | 1988-06-21 | Microcomputer equipment |
Applications Claiming Priority (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP62-158004 | 1987-06-25 | ||
JP15800487 | 1987-06-25 | ||
JP63153287A JPH0693235B2 (en) | 1987-06-25 | 1988-06-21 | Microcomputer equipment |
Publications (2)
Publication Number | Publication Date |
---|---|
JPS6478353A true JPS6478353A (en) | 1989-03-23 |
JPH0693235B2 JPH0693235B2 (en) | 1994-11-16 |
Family
ID=26481955
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP63153287A Expired - Lifetime JPH0693235B2 (en) | 1987-06-25 | 1988-06-21 | Microcomputer equipment |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPH0693235B2 (en) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPWO2004107188A1 (en) * | 2003-05-29 | 2006-07-20 | 富士通株式会社 | Data processing apparatus and data communication method |
Citations (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS61125670A (en) * | 1984-11-24 | 1986-06-13 | Olympus Optical Co Ltd | Data transfer device |
-
1988
- 1988-06-21 JP JP63153287A patent/JPH0693235B2/en not_active Expired - Lifetime
Patent Citations (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS61125670A (en) * | 1984-11-24 | 1986-06-13 | Olympus Optical Co Ltd | Data transfer device |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPWO2004107188A1 (en) * | 2003-05-29 | 2006-07-20 | 富士通株式会社 | Data processing apparatus and data communication method |
Also Published As
Publication number | Publication date |
---|---|
JPH0693235B2 (en) | 1994-11-16 |
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