JPS56152030A - Bus controlling system - Google Patents
Bus controlling systemInfo
- Publication number
- JPS56152030A JPS56152030A JP5507680A JP5507680A JPS56152030A JP S56152030 A JPS56152030 A JP S56152030A JP 5507680 A JP5507680 A JP 5507680A JP 5507680 A JP5507680 A JP 5507680A JP S56152030 A JPS56152030 A JP S56152030A
- Authority
- JP
- Japan
- Prior art keywords
- interruption
- level
- signal line
- interruptable
- bus
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/14—Handling requests for interconnection or transfer
- G06F13/20—Handling requests for interconnection or transfer for access to input/output bus
- G06F13/24—Handling requests for interconnection or transfer for access to input/output bus using interrupt
Landscapes
- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Bus Control (AREA)
Abstract
PURPOSE:To realize a fast bus by information all peripheral equipments of an interruptable level from CPU via a common signal line, by suppressing the interruption to an interruption factor lower than the interruptable level by each peripheral equipment and then by decreasing the number of signal lines below that of two systems. CONSTITUTION:Respective peripheral equipments 17 and CPU1 are connected together via interruptable-level signal line 2 and bus-use request signal line 3 requesting the use of bus 20, and CPU1 informs all equipments 17 of an interruptable level via signal line 2. In each equipment 17, comparing circuit 6 compares its interruption level signal 5 with the interruption level from signal line 2 to apply its output of a logic circuit, which performs logical operation between outputs of FFs 10 and 14 to suppress the interruption of an interruption factor lower than the interruption level from signal line 2, thereby outputting a request higher than the interruption level according to the outputs of FFs 10 and 14. Then, the number of signal lines 2 and 3 is decreased below that of two systems to realize faster processing than that of one system.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP5507680A JPS5935049B2 (en) | 1980-04-25 | 1980-04-25 | Bus control method |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP5507680A JPS5935049B2 (en) | 1980-04-25 | 1980-04-25 | Bus control method |
Publications (2)
Publication Number | Publication Date |
---|---|
JPS56152030A true JPS56152030A (en) | 1981-11-25 |
JPS5935049B2 JPS5935049B2 (en) | 1984-08-27 |
Family
ID=12988605
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP5507680A Expired JPS5935049B2 (en) | 1980-04-25 | 1980-04-25 | Bus control method |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS5935049B2 (en) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS6155771A (en) * | 1984-08-27 | 1986-03-20 | インタ−ナショナル ビジネス マシ−ンズ コ−ポレ−ション | Ruling apparatus and method |
-
1980
- 1980-04-25 JP JP5507680A patent/JPS5935049B2/en not_active Expired
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS6155771A (en) * | 1984-08-27 | 1986-03-20 | インタ−ナショナル ビジネス マシ−ンズ コ−ポレ−ション | Ruling apparatus and method |
Also Published As
Publication number | Publication date |
---|---|
JPS5935049B2 (en) | 1984-08-27 |
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