JPS5783864A - Multiprocessor system - Google Patents

Multiprocessor system

Info

Publication number
JPS5783864A
JPS5783864A JP55157672A JP15767280A JPS5783864A JP S5783864 A JPS5783864 A JP S5783864A JP 55157672 A JP55157672 A JP 55157672A JP 15767280 A JP15767280 A JP 15767280A JP S5783864 A JPS5783864 A JP S5783864A
Authority
JP
Japan
Prior art keywords
processor
bus
dma
transfer
memory
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP55157672A
Other languages
Japanese (ja)
Other versions
JPS6119056B2 (en
Inventor
Masahiro Takahashi
Kinshiro Onishi
Toshihiko Ogura
Hideo Watase
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP55157672A priority Critical patent/JPS5783864A/en
Publication of JPS5783864A publication Critical patent/JPS5783864A/en
Publication of JPS6119056B2 publication Critical patent/JPS6119056B2/ja
Granted legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F15/00—Digital computers in general; Data processing equipment in general
    • G06F15/16—Combinations of two or more digital computers each having at least an arithmetic unit, a program unit and a register, e.g. for a simultaneous processing of several programs
    • G06F15/163—Interprocessor communication
    • G06F15/167—Interprocessor communication using a common memory, e.g. mailbox

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Theoretical Computer Science (AREA)
  • Software Systems (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Multi Processors (AREA)
  • Information Transfer Systems (AREA)

Abstract

PURPOSE:To greatly increase the speed of data transfer, by transferring the data by memory access directly to a storage device that is the direct and final destination and covering over two processors. CONSTITUTION:A processor B consists of a CPU11, a memory 21, a processor bus b-2 and an input/output part having a direct memory access DMA function which performs an external interface; while a processor A consists of a CPU10, a memory 20 and a processor bus b-1 respectively. A gate circuit 36 connects the bus b-2 of the processor B to the bus b-1 of the processor A. The circuit 36 connects both buses and carries out the transfer of DMA when the DMA transfer is requested from the processor B to A based on the DMA function and in case both of the processors A and B do not occupy the buses b-1 and b-2 corresponding to each processor.
JP55157672A 1980-11-11 1980-11-11 Multiprocessor system Granted JPS5783864A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP55157672A JPS5783864A (en) 1980-11-11 1980-11-11 Multiprocessor system

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP55157672A JPS5783864A (en) 1980-11-11 1980-11-11 Multiprocessor system

Publications (2)

Publication Number Publication Date
JPS5783864A true JPS5783864A (en) 1982-05-25
JPS6119056B2 JPS6119056B2 (en) 1986-05-15

Family

ID=15654851

Family Applications (1)

Application Number Title Priority Date Filing Date
JP55157672A Granted JPS5783864A (en) 1980-11-11 1980-11-11 Multiprocessor system

Country Status (1)

Country Link
JP (1) JPS5783864A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS58217032A (en) * 1982-06-11 1983-12-16 Fuji Electric Co Ltd Terminal interface controlling system by multimicroprocessor
JPS5962960A (en) * 1982-10-02 1984-04-10 Horiba Ltd Data transfer circuit of computer

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS58217032A (en) * 1982-06-11 1983-12-16 Fuji Electric Co Ltd Terminal interface controlling system by multimicroprocessor
JPS5962960A (en) * 1982-10-02 1984-04-10 Horiba Ltd Data transfer circuit of computer

Also Published As

Publication number Publication date
JPS6119056B2 (en) 1986-05-15

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