JPS56110125A - Data processing device - Google Patents

Data processing device

Info

Publication number
JPS56110125A
JPS56110125A JP1244780A JP1244780A JPS56110125A JP S56110125 A JPS56110125 A JP S56110125A JP 1244780 A JP1244780 A JP 1244780A JP 1244780 A JP1244780 A JP 1244780A JP S56110125 A JPS56110125 A JP S56110125A
Authority
JP
Japan
Prior art keywords
data
buffer
module
controller
input
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP1244780A
Other languages
Japanese (ja)
Inventor
Hiroto Katsumata
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Tokyo Shibaura Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp, Tokyo Shibaura Electric Co Ltd filed Critical Toshiba Corp
Priority to JP1244780A priority Critical patent/JPS56110125A/en
Publication of JPS56110125A publication Critical patent/JPS56110125A/en
Pending legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/20—Handling requests for interconnection or transfer for access to input/output bus
    • G06F13/28—Handling requests for interconnection or transfer for access to input/output bus using burst mode transfer, e.g. direct memory access DMA, cycle steal

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Bus Control (AREA)

Abstract

PURPOSE:To simplify the circuit configuration by providing a data buffer, an input/ output device controller and a data transfer control module between the system bus and the system interface controller. CONSTITUTION:A data which has been sent out by the high-rank system 1 is input to the data buffer 12 through the input/output device controller 23. When it has been informed, the data transfer control DMA module 24 occupies the system bus 26. The module 24 reads out a data from the buffer 12, and stores it in the buffer memory provided in the local memory 22. Subsequently, when a data request signal of the controller 23 has been received, the DMA module 25 occupies the bus 26. The module 25 reads out a data from the buffer memory in the memory 22, and transfers it to the buffer in the controller 23. In this way, a data is transferred to the low- rank system 2 from the high-rank system 1. Also, it is transferred to the system 1 from the system 2 in the same by through the opposite path.
JP1244780A 1980-02-06 1980-02-06 Data processing device Pending JPS56110125A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP1244780A JPS56110125A (en) 1980-02-06 1980-02-06 Data processing device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1244780A JPS56110125A (en) 1980-02-06 1980-02-06 Data processing device

Publications (1)

Publication Number Publication Date
JPS56110125A true JPS56110125A (en) 1981-09-01

Family

ID=11805580

Family Applications (1)

Application Number Title Priority Date Filing Date
JP1244780A Pending JPS56110125A (en) 1980-02-06 1980-02-06 Data processing device

Country Status (1)

Country Link
JP (1) JPS56110125A (en)

Cited By (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5943427A (en) * 1982-09-01 1984-03-10 Nec Corp Input and output control system of information processor
JPS60640U (en) * 1983-06-13 1985-01-07 株式会社ユ−シン Parallel processing system for DMA processing and program measurement mode
JPS6075958A (en) * 1983-09-30 1985-04-30 Nec Corp Data relay distributor
JPS60120452A (en) * 1983-12-02 1985-06-27 Advantest Corp Data transmitting device
JPS61206346A (en) * 1985-03-11 1986-09-12 Fujitsu Ltd Data exchange equipment
JPS6314226A (en) * 1986-07-04 1988-01-21 Hitachi Ltd Data processor
JPH01100653A (en) * 1987-10-14 1989-04-18 Fuji Facom Corp System for transferring data of i/o processor
JP2009243263A (en) * 2009-07-29 2009-10-22 Maezawa Ind Inc Scale spacing adjusting bar screen, and drainage pump protective system having scale spacing adjusting bar screen

Cited By (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5943427A (en) * 1982-09-01 1984-03-10 Nec Corp Input and output control system of information processor
JPS60640U (en) * 1983-06-13 1985-01-07 株式会社ユ−シン Parallel processing system for DMA processing and program measurement mode
JPS6075958A (en) * 1983-09-30 1985-04-30 Nec Corp Data relay distributor
JPS60120452A (en) * 1983-12-02 1985-06-27 Advantest Corp Data transmitting device
JPS61206346A (en) * 1985-03-11 1986-09-12 Fujitsu Ltd Data exchange equipment
JPH0511453B2 (en) * 1985-03-11 1993-02-15 Fujitsu Ltd
JPS6314226A (en) * 1986-07-04 1988-01-21 Hitachi Ltd Data processor
JPH01100653A (en) * 1987-10-14 1989-04-18 Fuji Facom Corp System for transferring data of i/o processor
JP2009243263A (en) * 2009-07-29 2009-10-22 Maezawa Ind Inc Scale spacing adjusting bar screen, and drainage pump protective system having scale spacing adjusting bar screen

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