JPS56115546A - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JPS56115546A JPS56115546A JP1841680A JP1841680A JPS56115546A JP S56115546 A JPS56115546 A JP S56115546A JP 1841680 A JP1841680 A JP 1841680A JP 1841680 A JP1841680 A JP 1841680A JP S56115546 A JPS56115546 A JP S56115546A
- Authority
- JP
- Japan
- Prior art keywords
- layer
- type
- region
- impurity
- diffusion coefficient
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/74—Making of localized buried regions, e.g. buried collector layers, internal connections substrate contacts
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Element Separation (AREA)
- Bipolar Transistors (AREA)
Abstract
PURPOSE:To improve the electric characteristics of and to enhance the integration of the semiconductor device having a low resistance buried layer as a part of an element region by forming the buried layer of the first region with the first impurity and the second region with the second impurity having larger diffusion coefficient than that. CONSTITUTION:An N<-> type epitaxial collector layer 2 is formed on a P type substrate 1 and a P type base 6 and N type emitter 7 are sequentially formed on the surface of the layer 2 in the bipolar semiconductor device. N<+> type buried layers 3a, 3b are formed between the substrate 1 and the epitaxial layer 2. The diffusion coefficient of the impurity of the layer 3a is small, and the diffusion coefficient of the impurity of the layer 3b is large. A collector pickup N<+> type region 5 is connected to the layer 3b. Thus, the output resistance can be lowered and the expansion of the pickup region can be reduced. Accordingly, the integration can be reduced. This can be applied to the photoelectric conversion diode and the junction gate type FET having buried layer.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP1841680A JPS56115546A (en) | 1980-02-16 | 1980-02-16 | Semiconductor device |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP1841680A JPS56115546A (en) | 1980-02-16 | 1980-02-16 | Semiconductor device |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS56115546A true JPS56115546A (en) | 1981-09-10 |
Family
ID=11971046
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP1841680A Pending JPS56115546A (en) | 1980-02-16 | 1980-02-16 | Semiconductor device |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS56115546A (en) |
-
1980
- 1980-02-16 JP JP1841680A patent/JPS56115546A/en active Pending
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