JPS5550666A - Method of fabricating double gate mos-type integrated circuit - Google Patents
Method of fabricating double gate mos-type integrated circuitInfo
- Publication number
- JPS5550666A JPS5550666A JP12437278A JP12437278A JPS5550666A JP S5550666 A JPS5550666 A JP S5550666A JP 12437278 A JP12437278 A JP 12437278A JP 12437278 A JP12437278 A JP 12437278A JP S5550666 A JPS5550666 A JP S5550666A
- Authority
- JP
- Japan
- Prior art keywords
- layer
- pattern
- integrated circuit
- gate
- film
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Landscapes
- Semiconductor Memories (AREA)
- Non-Volatile Memory (AREA)
Abstract
PURPOSE: To provide a high packing density integrated circuit by growing bouble layers of not doped polycrystalline silicon on a semiconductor substrate, patterning the polycrystalline layer on the upper layer, and then implanting ion to the lower polycrystalline layer being exposed with the patterned layer as a mask to accelerate the etching speed.
CONSTITUTION: An SiO2 film 2 is coated on a p-type silicon substrate 1 to thereby grow not doped polycrystalline silicon layer 3 on the entire surface, and not doped polycrystalline silicon layer 5 is again accumulated through a SiO2 film 4 thereon. Then, a pattern 6 of resist film is provided on the predetermined region thereon, and with the pattern 6 as a mask it is wet etched to thereby retain a control gate 15 of the layer 5 only under the pattern 6. Then, with the pattern 6 and the gate 15 as masks impurities ion is implanted to the lower polycrystalline layer 3 to thus etch it while accelerating the etching speed at the portion to thereby obtain a gate of the layers 15 and 13. Then, the pattern 6 is removed.
COPYRIGHT: (C)1980,JPO&Japio
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP12437278A JPS5550666A (en) | 1978-10-09 | 1978-10-09 | Method of fabricating double gate mos-type integrated circuit |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP12437278A JPS5550666A (en) | 1978-10-09 | 1978-10-09 | Method of fabricating double gate mos-type integrated circuit |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS5550666A true JPS5550666A (en) | 1980-04-12 |
Family
ID=14883761
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP12437278A Pending JPS5550666A (en) | 1978-10-09 | 1978-10-09 | Method of fabricating double gate mos-type integrated circuit |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS5550666A (en) |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS5484098A (en) * | 1977-12-19 | 1979-07-04 | Kobayashi Shiyouyuten Yuugen | Production of low salt *miso* utilising *amazake* |
JPS63244685A (en) * | 1987-03-30 | 1988-10-12 | Nec Corp | Manufacture of semiconductor nonvolatile memory |
-
1978
- 1978-10-09 JP JP12437278A patent/JPS5550666A/en active Pending
Cited By (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS5484098A (en) * | 1977-12-19 | 1979-07-04 | Kobayashi Shiyouyuten Yuugen | Production of low salt *miso* utilising *amazake* |
JPS5625101B2 (en) * | 1977-12-19 | 1981-06-10 | ||
JPS63244685A (en) * | 1987-03-30 | 1988-10-12 | Nec Corp | Manufacture of semiconductor nonvolatile memory |
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