JPS5550650A - Semiconductor device - Google Patents

Semiconductor device

Info

Publication number
JPS5550650A
JPS5550650A JP12381778A JP12381778A JPS5550650A JP S5550650 A JPS5550650 A JP S5550650A JP 12381778 A JP12381778 A JP 12381778A JP 12381778 A JP12381778 A JP 12381778A JP S5550650 A JPS5550650 A JP S5550650A
Authority
JP
Japan
Prior art keywords
chips
bonded
electric insulating
member material
thermal conductivity
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP12381778A
Other languages
Japanese (ja)
Inventor
Yoshihiko Niimura
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mitsubishi Electric Corp
Original Assignee
Mitsubishi Electric Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsubishi Electric Corp filed Critical Mitsubishi Electric Corp
Priority to JP12381778A priority Critical patent/JPS5550650A/en
Publication of JPS5550650A publication Critical patent/JPS5550650A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item

Landscapes

  • Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)

Abstract

PURPOSE: To improve thermal equilibrium among a plurality of semiconductor chips, by thermally uniting a plurality of electrode leads, to which the said chips are each bonded, by means of a member material of electric insulating property and of high thermal conductivity.
CONSTITUTION: The electrodes 3W8 of two transistor chips 1, 2 are bonded to the ceramics 14 of a combining member material of high thermal conductivity and electric insulating properties. Thus, thermal equilibrium can excellently be maintained.
COPYRIGHT: (C)1980,JPO&Japio
JP12381778A 1978-10-06 1978-10-06 Semiconductor device Pending JPS5550650A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP12381778A JPS5550650A (en) 1978-10-06 1978-10-06 Semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP12381778A JPS5550650A (en) 1978-10-06 1978-10-06 Semiconductor device

Publications (1)

Publication Number Publication Date
JPS5550650A true JPS5550650A (en) 1980-04-12

Family

ID=14870070

Family Applications (1)

Application Number Title Priority Date Filing Date
JP12381778A Pending JPS5550650A (en) 1978-10-06 1978-10-06 Semiconductor device

Country Status (1)

Country Link
JP (1) JPS5550650A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS58500187A (en) * 1981-02-07 1983-02-03 モトロ−ラ・インコ−ポレ−テツド High current package with multi-level leads

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS58500187A (en) * 1981-02-07 1983-02-03 モトロ−ラ・インコ−ポレ−テツド High current package with multi-level leads

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