JPS5692474A - Aging tester of ic - Google Patents

Aging tester of ic

Info

Publication number
JPS5692474A
JPS5692474A JP17009979A JP17009979A JPS5692474A JP S5692474 A JPS5692474 A JP S5692474A JP 17009979 A JP17009979 A JP 17009979A JP 17009979 A JP17009979 A JP 17009979A JP S5692474 A JPS5692474 A JP S5692474A
Authority
JP
Japan
Prior art keywords
ics
printed board
open connectors
terminals
plug plates
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP17009979A
Other languages
Japanese (ja)
Inventor
Tetsuya Shimada
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Usac Electronic Ind Co Ltd
Original Assignee
Usac Electronic Ind Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Usac Electronic Ind Co Ltd filed Critical Usac Electronic Ind Co Ltd
Priority to JP17009979A priority Critical patent/JPS5692474A/en
Publication of JPS5692474A publication Critical patent/JPS5692474A/en
Pending legal-status Critical Current

Links

Landscapes

  • Testing Of Individual Semiconductor Devices (AREA)

Abstract

PURPOSE: To enable various kinds of ICs to be tested easily only through mounting operation of plug plates by mounting the plug plates to open connectors thereby forming a testing circuit relating to all the ICs on a substrate.
CONSTITUTION: Open connectors 6 are disposed between IC sockets 2 on a printed board 1, and plug plates 7 are embedded in these open connectors 6. The open connectors 6 are interspersedly disposed over the entire surface of the printed board 1. A plurality of terminals of the printed wires connected to the input terminals of ICs are led out to the side part 1c of the printed board 1 from the terminal T1 up to Tn, and signals are applied from an oscillator OSC to these terminals T1WTn.
COPYRIGHT: (C)1981,JPO&Japio
JP17009979A 1979-12-25 1979-12-25 Aging tester of ic Pending JPS5692474A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP17009979A JPS5692474A (en) 1979-12-25 1979-12-25 Aging tester of ic

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP17009979A JPS5692474A (en) 1979-12-25 1979-12-25 Aging tester of ic

Publications (1)

Publication Number Publication Date
JPS5692474A true JPS5692474A (en) 1981-07-27

Family

ID=15898613

Family Applications (1)

Application Number Title Priority Date Filing Date
JP17009979A Pending JPS5692474A (en) 1979-12-25 1979-12-25 Aging tester of ic

Country Status (1)

Country Link
JP (1) JPS5692474A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH04198776A (en) * 1990-11-28 1992-07-20 Mitsubishi Electric Corp Burn-in device
CN105301403A (en) * 2015-11-16 2016-02-03 宁波工程学院 Timer aging test monitoring device

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH04198776A (en) * 1990-11-28 1992-07-20 Mitsubishi Electric Corp Burn-in device
CN105301403A (en) * 2015-11-16 2016-02-03 宁波工程学院 Timer aging test monitoring device
CN105301403B (en) * 2015-11-16 2018-09-11 宁波工程学院 A kind of timer burn-in test monitoring device

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