JPS5758296A - Semiconductor memory - Google Patents

Semiconductor memory

Info

Publication number
JPS5758296A
JPS5758296A JP56119063A JP11906381A JPS5758296A JP S5758296 A JPS5758296 A JP S5758296A JP 56119063 A JP56119063 A JP 56119063A JP 11906381 A JP11906381 A JP 11906381A JP S5758296 A JPS5758296 A JP S5758296A
Authority
JP
Japan
Prior art keywords
cell
lines
memory
signal
differential
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP56119063A
Other languages
Japanese (ja)
Inventor
Kiyoo Ito
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP56119063A priority Critical patent/JPS5758296A/en
Publication of JPS5758296A publication Critical patent/JPS5758296A/en
Pending legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/18—Bit line organisation; Bit line lay-out

Landscapes

  • Static Random-Access Memory (AREA)

Abstract

PURPOSE:To realize a high speed memory LSI capable of highly stable operation, by closely locating digit lines which are differentially detected each other. CONSTITUTION:Data lines D0, -D0 on which differential readout signals appear, provided closely in parallel, and a memory cell MC is connected only one cross point among cross points D0, -D0 and each word lines W, DW. In reading out a memory, the D0, -D0 are precharged to the same voltage, the said W is selected to readout a cell, and the DW is selected and a dummy cell DM connected to the -D0 not connected to the cell is read out at the same time and a differential voltage appeared on the D0,-D0 is differentially amplified with a preamplifer PA. The signal from the PA is applied to an amplifier MA via transistors Q0, -Q0 which turn on through the application of an address signal A, and common signal lines CD, -CD.
JP56119063A 1981-07-31 1981-07-31 Semiconductor memory Pending JPS5758296A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP56119063A JPS5758296A (en) 1981-07-31 1981-07-31 Semiconductor memory

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP56119063A JPS5758296A (en) 1981-07-31 1981-07-31 Semiconductor memory

Related Parent Applications (1)

Application Number Title Priority Date Filing Date
JP14805674A Division JPS5539073B2 (en) 1974-12-25 1974-12-25

Publications (1)

Publication Number Publication Date
JPS5758296A true JPS5758296A (en) 1982-04-07

Family

ID=14751977

Family Applications (1)

Application Number Title Priority Date Filing Date
JP56119063A Pending JPS5758296A (en) 1981-07-31 1981-07-31 Semiconductor memory

Country Status (1)

Country Link
JP (1) JPS5758296A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH01245488A (en) * 1988-03-28 1989-09-29 Nec Corp Random access memory
US6953301B2 (en) 2002-02-14 2005-10-11 Hinode, Ltd. Lid assembly for facility access opening

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH01245488A (en) * 1988-03-28 1989-09-29 Nec Corp Random access memory
US6953301B2 (en) 2002-02-14 2005-10-11 Hinode, Ltd. Lid assembly for facility access opening

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