JPS5514588A - Semiconductor dynamic memory unit - Google Patents

Semiconductor dynamic memory unit

Info

Publication number
JPS5514588A
JPS5514588A JP8811078A JP8811078A JPS5514588A JP S5514588 A JPS5514588 A JP S5514588A JP 8811078 A JP8811078 A JP 8811078A JP 8811078 A JP8811078 A JP 8811078A JP S5514588 A JPS5514588 A JP S5514588A
Authority
JP
Japan
Prior art keywords
information
sets
line
charge
output
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP8811078A
Other languages
Japanese (ja)
Inventor
Toru Furuyama
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Tokyo Shibaura Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp, Tokyo Shibaura Electric Co Ltd filed Critical Toshiba Corp
Priority to JP8811078A priority Critical patent/JPS5514588A/en
Publication of JPS5514588A publication Critical patent/JPS5514588A/en
Pending legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/56—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency
    • G11C11/565—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency using capacitive charge storage elements
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/06—Sense amplifiers; Associated circuits, e.g. timing or triggering circuits

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)

Abstract

PURPOSE:To enable high density, by memorizing one memory cell with multi-value information ternary or more. CONSTITUTION:The stored charge of the memory cell MC is classified into n(greater than 2) sets of steps to discriminate to which part of the n sets of steps the charge belongs. For example, the information 0,1,2...,n-1 is determined to which part of the potential well the charge is stored. Further, at the information discrimination, MOSFET of MC is driven with the word line WL, the information is delivered to the bit line BL, the line BL is connected to three sets of the sense circuits SAi, each output is fed to the output buffer OB1 via the input and output line I/O i, and the outputs Dout1, Dout2 corresponding to the combination of the I/O i state are obtained.
JP8811078A 1978-07-19 1978-07-19 Semiconductor dynamic memory unit Pending JPS5514588A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP8811078A JPS5514588A (en) 1978-07-19 1978-07-19 Semiconductor dynamic memory unit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP8811078A JPS5514588A (en) 1978-07-19 1978-07-19 Semiconductor dynamic memory unit

Publications (1)

Publication Number Publication Date
JPS5514588A true JPS5514588A (en) 1980-02-01

Family

ID=13933733

Family Applications (1)

Application Number Title Priority Date Filing Date
JP8811078A Pending JPS5514588A (en) 1978-07-19 1978-07-19 Semiconductor dynamic memory unit

Country Status (1)

Country Link
JP (1) JPS5514588A (en)

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR2506057A1 (en) * 1981-05-13 1982-11-19 Hitachi Ltd SEMICONDUCTOR MEMORY
EP0148488A2 (en) * 1983-12-23 1985-07-17 Hitachi, Ltd. Semiconductor memory having multiple level storage structure
JPS62192999A (en) * 1986-02-18 1987-08-24 インタ−ナショナル　ビジネス　マシ−ンズ　コ−ポレ−ション Sensing circuit for multiplex level memory
JPS63149900A (en) * 1986-12-15 1988-06-22 Toshiba Corp Semiconductor memory
JP2011501340A (en) * 2007-10-15 2011-01-06 エス． アクア セミコンダクター， エルエルシー Multilevel memory storage device having two gate transistors
JP2017118141A (en) * 2010-10-20 2017-06-29 株式会社半導体エネルギー研究所 Storage device

Cited By (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR2506057A1 (en) * 1981-05-13 1982-11-19 Hitachi Ltd SEMICONDUCTOR MEMORY
EP0148488A2 (en) * 1983-12-23 1985-07-17 Hitachi, Ltd. Semiconductor memory having multiple level storage structure
JPS62192999A (en) * 1986-02-18 1987-08-24 インタ−ナショナル　ビジネス　マシ−ンズ　コ−ポレ−ション Sensing circuit for multiplex level memory
JPH0468718B2 (en) * 1986-02-18 1992-11-04 Intaanashonaru Bijinesu Mashiinzu Corp
JPS63149900A (en) * 1986-12-15 1988-06-22 Toshiba Corp Semiconductor memory
EP0273639A2 (en) * 1986-12-15 1988-07-06 Kabushiki Kaisha Toshiba Semiconductor memory having multiple level storage structure
JPH059878B2 (en) * 1986-12-15 1993-02-08 Tokyo Shibaura Electric Co
JP2011501340A (en) * 2007-10-15 2011-01-06 エス． アクア セミコンダクター， エルエルシー Multilevel memory storage device having two gate transistors
JP2017118141A (en) * 2010-10-20 2017-06-29 株式会社半導体エネルギー研究所 Storage device

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