JPS5654695A - Associative memory device - Google Patents

Associative memory device

Info

Publication number
JPS5654695A
JPS5654695A JP12977179A JP12977179A JPS5654695A JP S5654695 A JPS5654695 A JP S5654695A JP 12977179 A JP12977179 A JP 12977179A JP 12977179 A JP12977179 A JP 12977179A JP S5654695 A JPS5654695 A JP S5654695A
Authority
JP
Japan
Prior art keywords
mode
retrieving
memory
associative
signal
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP12977179A
Other languages
Japanese (ja)
Other versions
JPS6045504B2 (en
Inventor
Tadanobu Nikaido
Takeshi Ogura
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Nippon Telegraph and Telephone Corp
Original Assignee
Nippon Telegraph and Telephone Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Nippon Telegraph and Telephone Corp filed Critical Nippon Telegraph and Telephone Corp
Priority to JP12977179A priority Critical patent/JPS6045504B2/en
Publication of JPS5654695A publication Critical patent/JPS5654695A/en
Publication of JPS6045504B2 publication Critical patent/JPS6045504B2/en
Expired legal-status Critical Current

Links

Landscapes

  • Memory System Of A Hierarchy Structure (AREA)
  • Data Exchanges In Wide-Area Networks (AREA)

Abstract

PURPOSE: To increase the number of bits for each word and then reduce the number of signal terminals, by using the address information of the writing mode in the form of the retrieving mode.
CONSTITUTION: An associative process is carried out between the retrieving data and the memory information stored in the memory, and the result of this associative process is delivered in correspondence of words. In this case, the mode designation signal 11 becomes 1 in the read/write mode to activate the gates 7W10, and the output of the decoded 2 address information is connected to the designated word line among 12W 15 to perform the reading and writing via the input/output data line 17. On the other hand, in the retrieving mode, the signal 11 becomes 0 with the word lines 12W15 turned to 0, and the associative memory cell arrays 18W21 compare the retrieving data applied to the retrieving data line 16 with the memory data. And 1 is delivered to the detection signal lines 22W25 when a coincidence is obtained in the above comparison.
COPYRIGHT: (C)1981,JPO&Japio
JP12977179A 1979-10-08 1979-10-08 associative memory device Expired JPS6045504B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP12977179A JPS6045504B2 (en) 1979-10-08 1979-10-08 associative memory device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP12977179A JPS6045504B2 (en) 1979-10-08 1979-10-08 associative memory device

Publications (2)

Publication Number Publication Date
JPS5654695A true JPS5654695A (en) 1981-05-14
JPS6045504B2 JPS6045504B2 (en) 1985-10-09

Family

ID=15017797

Family Applications (1)

Application Number Title Priority Date Filing Date
JP12977179A Expired JPS6045504B2 (en) 1979-10-08 1979-10-08 associative memory device

Country Status (1)

Country Link
JP (1) JPS6045504B2 (en)

Also Published As

Publication number Publication date
JPS6045504B2 (en) 1985-10-09

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