JPS5493965A - Semiconductor vessel - Google Patents

Semiconductor vessel

Info

Publication number
JPS5493965A
JPS5493965A JP74978A JP74978A JPS5493965A JP S5493965 A JPS5493965 A JP S5493965A JP 74978 A JP74978 A JP 74978A JP 74978 A JP74978 A JP 74978A JP S5493965 A JPS5493965 A JP S5493965A
Authority
JP
Japan
Prior art keywords
area
region
metallized
insulating substrate
semiconductor
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP74978A
Other languages
Japanese (ja)
Inventor
Shuichi Osaka
Takashi Kondo
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mitsubishi Electric Corp
Original Assignee
Mitsubishi Electric Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsubishi Electric Corp filed Critical Mitsubishi Electric Corp
Priority to JP74978A priority Critical patent/JPS5493965A/en
Publication of JPS5493965A publication Critical patent/JPS5493965A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/04Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554External layer
    • H01L2224/0555Shape
    • H01L2224/05552Shape in top view
    • H01L2224/05553Shape in top view being rectangular
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491Disposition
    • H01L2224/4912Layout
    • H01L2224/49171Fan-out arrangements

Landscapes

  • Wire Bonding (AREA)

Abstract

PURPOSE: To reduce the thermal resistance of a semiconductor vessel and further shorten the length of a metallic narrow wire by making the area of a metallized region on the first insulating substrate larger than the area of the aperture part of the second insulating substrate.
CONSTITUTION: Insulating substrate 6 equipped with aperture part 4 and plural metallized leads 5 is provided on the first insulating substrate 1. Then, metallized region 3 is so provided that semiconductor element 2 may be fixed onto substrate 1. Furhter, electrode 7 of this element 2 and metallized lead 5 are connected by metallic narrow wire 8. In this case, the area of metallized region 3 is made larger than the area of aperture 4 so that region 3 may reache a region where substrates 1 and 6 overlap. As a result, since tha area of metallized region 3 becomes large and thermal resistance is reduced, the maximum temperature of the semiconductor device can be made lower. Further, since the length of metallic narrow wire 8 can be made short, the connection work for metallic narrow wires becomes easy, and the short-circuit to others can be prevented.
COPYRIGHT: (C)1979,JPO&Japio
JP74978A 1978-01-06 1978-01-06 Semiconductor vessel Pending JPS5493965A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP74978A JPS5493965A (en) 1978-01-06 1978-01-06 Semiconductor vessel

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP74978A JPS5493965A (en) 1978-01-06 1978-01-06 Semiconductor vessel

Publications (1)

Publication Number Publication Date
JPS5493965A true JPS5493965A (en) 1979-07-25

Family

ID=11482337

Family Applications (1)

Application Number Title Priority Date Filing Date
JP74978A Pending JPS5493965A (en) 1978-01-06 1978-01-06 Semiconductor vessel

Country Status (1)

Country Link
JP (1) JPS5493965A (en)

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