JPS5434728A - Input/output control system - Google Patents

Input/output control system

Info

Publication number
JPS5434728A
JPS5434728A JP10186277A JP10186277A JPS5434728A JP S5434728 A JPS5434728 A JP S5434728A JP 10186277 A JP10186277 A JP 10186277A JP 10186277 A JP10186277 A JP 10186277A JP S5434728 A JPS5434728 A JP S5434728A
Authority
JP
Japan
Prior art keywords
input
control system
output control
cpu
control memory
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP10186277A
Other languages
Japanese (ja)
Other versions
JPS605986B2 (en
Inventor
Takashi Ishikawa
Akira Onodera
Saneyuki Hiwatari
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP52101862A priority Critical patent/JPS605986B2/en
Publication of JPS5434728A publication Critical patent/JPS5434728A/en
Publication of JPS605986B2 publication Critical patent/JPS605986B2/en
Expired legal-status Critical Current

Links

Abstract

PURPOSE: To enable the data transfer between CPU and the control memory by deciding whether or not the subchannel control memory can be given an access directly from CPU and changing the maintenance address detecting part effective in case the direct access is impossible.
COPYRIGHT: (C)1979,JPO&Japio
JP52101862A 1977-08-24 1977-08-24 Input/output control method Expired JPS605986B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP52101862A JPS605986B2 (en) 1977-08-24 1977-08-24 Input/output control method

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP52101862A JPS605986B2 (en) 1977-08-24 1977-08-24 Input/output control method

Publications (2)

Publication Number Publication Date
JPS5434728A true JPS5434728A (en) 1979-03-14
JPS605986B2 JPS605986B2 (en) 1985-02-15

Family

ID=14311806

Family Applications (1)

Application Number Title Priority Date Filing Date
JP52101862A Expired JPS605986B2 (en) 1977-08-24 1977-08-24 Input/output control method

Country Status (1)

Country Link
JP (1) JPS605986B2 (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0474243A (en) * 1990-07-17 1992-03-09 Toshiba Corp On-line diagnostic system for multiplex memory device

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0474243A (en) * 1990-07-17 1992-03-09 Toshiba Corp On-line diagnostic system for multiplex memory device

Also Published As

Publication number Publication date
JPS605986B2 (en) 1985-02-15

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