JPS5486287A - Integrated-circuit device - Google Patents

Integrated-circuit device

Info

Publication number
JPS5486287A
JPS5486287A JP15482277A JP15482277A JPS5486287A JP S5486287 A JPS5486287 A JP S5486287A JP 15482277 A JP15482277 A JP 15482277A JP 15482277 A JP15482277 A JP 15482277A JP S5486287 A JPS5486287 A JP S5486287A
Authority
JP
Japan
Prior art keywords
film
layer
wiring
films
pattern
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP15482277A
Other languages
Japanese (ja)
Other versions
JPS6138611B2 (en
Inventor
Toshio Wada
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp, Nippon Electric Co Ltd filed Critical NEC Corp
Priority to JP15482277A priority Critical patent/JPS5486287A/en
Publication of JPS5486287A publication Critical patent/JPS5486287A/en
Publication of JPS6138611B2 publication Critical patent/JPS6138611B2/ja
Granted legal-status Critical Current

Links

Landscapes

  • Electrodes Of Semiconductors (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

PURPOSE: To accelerate the operation speed of an IC by making the density high with the pattern effective area rate increased by providing an insulating film made of the substance of the 1st layer conductive wiring to the part where the 1st layer conductive wiring and 2nd layer conductive wiring confront each other.
CONSTITUTION: On the surface of P-type Si substrate 31, N-type regions 32, 32' and 32" are diffusion-formed, the 1st layer Al wiring patterns 22 and 22' are provided throgh SiO2 films 33 and 33', and SiO2 film 34 is adhered to the entire surface. On film 34, photo resist film 35 is applied, opening pattern 36 is made, and film 35 is used as a mask to etching-remove film 34 on region 32'. Then,film 35 is used as a mask for anode oxidation, exposed wirings 22 and 22' are converted into unporous Al2O3 films 37 and 37' being self-matched, and after film 35 is removed, the 2nd layer Al wiring pattern 24 is formed. In this way, the 2nd layer Al wiring 24 is obtained which makes conductive coupling with region 32' between the 1st layer Al wirings 22 and 22' and is insulated from the lower layer via films 37 and 37' and 34.
COPYRIGHT: (C)1979,JPO&Japio
JP15482277A 1977-12-21 1977-12-21 Integrated-circuit device Granted JPS5486287A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP15482277A JPS5486287A (en) 1977-12-21 1977-12-21 Integrated-circuit device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP15482277A JPS5486287A (en) 1977-12-21 1977-12-21 Integrated-circuit device

Publications (2)

Publication Number Publication Date
JPS5486287A true JPS5486287A (en) 1979-07-09
JPS6138611B2 JPS6138611B2 (en) 1986-08-30

Family

ID=15592623

Family Applications (1)

Application Number Title Priority Date Filing Date
JP15482277A Granted JPS5486287A (en) 1977-12-21 1977-12-21 Integrated-circuit device

Country Status (1)

Country Link
JP (1) JPS5486287A (en)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS63133708U (en) * 1987-02-24 1988-09-01

Also Published As

Publication number Publication date
JPS6138611B2 (en) 1986-08-30

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