JPS5562750A - Semiconductor integrated circuit device - Google Patents
Semiconductor integrated circuit deviceInfo
- Publication number
- JPS5562750A JPS5562750A JP13644778A JP13644778A JPS5562750A JP S5562750 A JPS5562750 A JP S5562750A JP 13644778 A JP13644778 A JP 13644778A JP 13644778 A JP13644778 A JP 13644778A JP S5562750 A JPS5562750 A JP S5562750A
- Authority
- JP
- Japan
- Prior art keywords
- film
- sio
- substrate
- wiring
- polycrystalline silicon
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Landscapes
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
PURPOSE: To flatten the surface of a semiconductor integrated circuit by altering the portion except for the first polycrystalline layer wired portion when forming a multilayer wiring using polycrystalline silicon into an oxide film and providing the second polycrystalline silicon wiring thereon.
CONSTITUTION: A thick field SiO2 film 18 is formed on both ends of an N-type silicon substrate 17, a thin gate SiO2 film 19 of predetermined shape is provided on the substrate 17 surrounded by the film 18, first aligning polycrystalline silicon wiring 20 is accumulated on the entire surface thereof to thus coat it with SiO2 film 21 and Si3N4 film 22. Then, a pattern of resist film 23 is provided thereon, the films 22 and 21 and wiring 20 are etched with the pattern as a mask, and a P+-type region 24 is diffused in the substrate 17 using the opening thus perforated. Then, the film 23 is removed, the film 21 of exposed portion is altered to a SiO2 film 25 with the film 22 as a mask, and the residual films 22 and 21 are then removed to then diffuse a P+-type region 26 in the substrate 17. Then, a second aligning polycrystalline silicon wiring 28 is accumulated on predetermined region while interposing the SiO2 film 27 to coat it with SiO2 film 29 and Si2N4 film 30.
COPYRIGHT: (C)1980,JPO&Japio
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP13644778A JPS5562750A (en) | 1978-11-06 | 1978-11-06 | Semiconductor integrated circuit device |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP13644778A JPS5562750A (en) | 1978-11-06 | 1978-11-06 | Semiconductor integrated circuit device |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS5562750A true JPS5562750A (en) | 1980-05-12 |
Family
ID=15175316
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP13644778A Pending JPS5562750A (en) | 1978-11-06 | 1978-11-06 | Semiconductor integrated circuit device |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS5562750A (en) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS57162351A (en) * | 1981-03-16 | 1982-10-06 | Fairchild Camera Instr Co | Two-dimensional germanium-silicon mutual connector and electrode for integrated circuit |
Citations (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS5396769A (en) * | 1977-02-04 | 1978-08-24 | Nippon Telegr & Teleph Corp <Ntt> | Production of mis integratd circuit |
-
1978
- 1978-11-06 JP JP13644778A patent/JPS5562750A/en active Pending
Patent Citations (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS5396769A (en) * | 1977-02-04 | 1978-08-24 | Nippon Telegr & Teleph Corp <Ntt> | Production of mis integratd circuit |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS57162351A (en) * | 1981-03-16 | 1982-10-06 | Fairchild Camera Instr Co | Two-dimensional germanium-silicon mutual connector and electrode for integrated circuit |
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