JPH1197476A - 半導体装置及びその製造方法 - Google Patents

半導体装置及びその製造方法

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Publication number
JPH1197476A
JPH1197476A JP9256994A JP25699497A JPH1197476A JP H1197476 A JPH1197476 A JP H1197476A JP 9256994 A JP9256994 A JP 9256994A JP 25699497 A JP25699497 A JP 25699497A JP H1197476 A JPH1197476 A JP H1197476A
Authority
JP
Japan
Prior art keywords
chip
lead
wire
semiconductor device
pad
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP9256994A
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English (en)
Other versions
JP2954109B2 (ja
Inventor
Naoto Kimura
直人 木村
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Kyushu Ltd
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NEC Kyushu Ltd
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Application filed by NEC Kyushu Ltd filed Critical NEC Kyushu Ltd
Priority to JP9256994A priority Critical patent/JP2954109B2/ja
Publication of JPH1197476A publication Critical patent/JPH1197476A/ja
Application granted granted Critical
Publication of JP2954109B2 publication Critical patent/JP2954109B2/ja
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

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  • Power Engineering (AREA)
  • Wire Bonding (AREA)

Abstract

(57)【要約】 【課題】従来の半導体装置では、ワイヤボンディングは
チップ上のパッドから始まっており、チップ角でのチッ
プとワイヤの接触を回避するために、バッケージサイズ
が小さくならないという欠点があった。 【解決手段】チップ１０１内のパッド１０２に予め金ボ
ール１０３を形成しておき、チップ１０１の近傍のリー
ド上の点１０５ｎからパッド１０２上の金ボール１０３
と接着させる方法を採ることにより、ワイヤボンデイン
グの位置をチップ端１０１ｂに近づけられるので、バッ
ケージサイズを小さく出来る。

Description

【発明の詳細な説明】
【０００１】
【発明の属する技術分野】本発明は半導体装置に関し、
特にＣＯＬ（チップ・オン・リード）構造のＢＧＡ（ボ
ール・グリッド・アレイ）型ＣＳＰ（チップ・サイズ・
パッケージ）半導体装置及び半導体装置製造方法に関す
る。
【０００２】
【従来の技術】従来、ＣＯＬ（チップ・オン・リード）
構造のＢＧＡ（ボール・グリッド・アレイ）型ＣＳＰ
（チップ・サイズ・パッケージ）半導体装置は、図３の
断面図に示すように、リード２０５と、このリード２０
５上に搭載されたチップ１０１と、リード２０５とチッ
プ１０１内のパッド１０２とをパッド１０２を始点とし
リード２０５を終点として行われるワイヤボンディング
によって接続するワイヤ２０４と、チップ１０１とリー
ド２０５とワイヤ２０４とを封止する樹脂２０７と、リ
ード２０５にチップ１０１の裏面側に接着テープ１０６
で接着される半田ボール１０８とから成り、全体として
パッケージ２０９を構成している。
【０００３】この従来例においては、最初のワイヤボン
ディングはパッド１０２から始まっていて、パッド１０
２上方では上方部分２０４ｕの如くワイヤ２０４がほぼ
垂直となっているが、ワイヤボンディングの終点２０５
ｔに向かうワイヤ部分２０４ｇは終点に向かって長くな
だらかな形状となる。
【０００４】
【発明が解決しようとする課題】上述したように、従来
のＣＯＬ構造のＢＧＡ型ＣＳＰ半導体装置ではバッケー
ジサイズが小さくならないということである。従来の構
造においては、ワイヤボンディング工程においてワイヤ
ボンディングをチップ１０１内のパッド１０２からリー
ド２０５に向かつて行うが、ワイヤ２０４はパッド２０
２の上方部分２０４ｕではほぼ垂直になるが、リード２
０５上のワイヤボンディング終点２０５ｔに向かう部分
のワイヤ形状２０４ｇはなだらかで長い形状にならざる
を得ず、チップ端１０１ｂからリード端２０５ｂまでの
距離が長くなり、結果的にパッケージサイズが大きくな
ってしまっていた。
【０００５】本発明の目的は、小型化したＣＯＬ構造の
ＢＧＡ型半導体装置を提供することにある。
【０００６】
【課題を解決するための手段】本発明の半導体装置は、
チップ近傍のリード上の点を起点とし、チップのパッド
を終点として、前記リードと前記パッドとをワイヤによ
り接続し、前記チップ、前記ワイヤ、前記リードを樹脂
被覆し、前記リードを前記樹脂の長さに切断し、前記チ
ップの裏面に位置するよう前記リード上の一部に半田ボ
ールを形成したことを特徴とする。
【０００７】
【発明の実施の形態】本発明の実施形態につき、図１
（ａ）、（ｂ）及び図２（ａ）〜（ｄ）を参照して説明
する。図１（ａ）は本発明の平面図を示し、リード１０
５はチップ１０１の下に複数本敷設されている。図１
（ｂ）は図１（ａ）のＸＸ線での断面図を示し、リード
１０５の下方には半田ボール１０８が接着されている。
チップ１０１は接着テープ１０６によりリード１０５に
接着されている。パッド１０２には金ボール１０３が接
着されており、リード１０５上のワイヤボンディング始
点１０５ｎからワイヤ１０４がワイヤボンディングによ
り金ボール１０３に接着されている。チップ１０１、ワ
イヤ１０４、リード１０５を含む主要部分は樹脂１０７
により被覆成形され、パッケージ１０９を形成してい
る。
【０００８】図２（ａ）〜（ｄ）は本実施形態の製造方
法を示す断面図である。まず，図２（ａ）に示すよう
に、キャピラリ１１０の中を通してワイヤ１０４がパッ
ド１０２に通常のワイヤボンディングにより圧着され
る。次に、図２（ｂ）に示すように金ボール１０３を残
してワイヤ１０４を切断し、パッド１０２の上に金ボー
ル１０３を形成する。この後、図２（ｃ）のように、チ
ップ１０１の端１０１ｂから９０μｍ〜１５０μｍに位
置するリード１０５上の点１０５ｎを起点として、そこ
から垂直にワイヤボンディングを行い、図２（ｄ）のよ
うにパッド１０２の上の金ボール１０３に接着する。
【０００９】従来のワイヤボンディングは図３に示すよ
うに、ワイヤがチップ内のパッドからワイヤボンディン
グされるために、ワイヤがチップ角１０１ｅに接触しな
いように、パッド２０２のすぐ上ではワイヤがほぼ垂直
の形状に形成され、ワイヤの終点に向かって長くなだら
かなカーブを描くよう形成される必要があり、リード上
のワイヤボンディングの終点を、チップの端から遠く離
して(チップの端から６００μｍ以上)設定しなければな
らない。このために、リードの終端が、チップの端から
ワイヤの長さに合わせて遠くなる必要と、樹脂で被覆す
べき領域、即ち、パッケージの長さがリード方向に長く
なる必要があった。
【００１０】一方、本実施形態の半導体装置は、 図１
（ｂ）のように、ワイヤをチップの端から９０μｍ〜１
５０μｍと、チップの端に近接したリード上の点から垂
直にワイヤボンディングできるためにリードの長さをリ
ード端１０５ｂまでと、短くすることができ、パッケー
ジの大きさを小さくすることができる。
【００１１】
【発明の効果】以上説明したように、本発明の構成によ
れば、ボンディングワイヤをチップの端部に近接して配
置でき、また、チップの端に近接したリード上の点から
垂直にワイヤボンディングできるためにリードの長さを
短くすることができ、パッケージの大きさを小さくする
ことができる、という効果がある。
【図面の簡単な説明】
【図１】（ａ）、（ｂ）は本発明の実施形態の半導体装
置の半田ボール形成直後の平面図及びそのＸＸ線におけ
る断面図である。
【図２】本発明の実施形態のワイヤボンデイング工程を
工程順に示す断面図である。
【図３】従来の技術により形成されたＣＯＬ構造のＢＧ
Ａ型ＣＳＰ半導体装置の断面図である。
【符号の説明】
１０１ チップ １０１ｂ チップ端 １０１ｅ チップ角 １０２ パッド １０３ 金ボール １０４、２０４ ワイヤ ２０４ｇ ワイヤボンデイング終点に向かう部分のワ
イヤ形状 ２０４ｕ パッド直上のワイヤ １０５、２０５ リード １０５ｎ チップ端に近接するリード上のワイヤボン
ディング始点 １０５ｂ、２０５ｂ リード端 ２０５ｔ リード上のワイヤボンディング終点 １０６ 接着テープ １０７、２０７ 樹脂 １０８ 半田ボール １０９、２０９ パッケージ １１０ キャピラリ

Claims (6)

    【特許請求の範囲】
  1. 【請求項１】 チップ・オン・リード構造のボール・グ
    リッド・アレイ型半導体装置において、チップ近傍のリ
    ード上の点を起点とし、そのチップ上のパッドを終点と
    して、前記リードと前記パッドとをワイヤにより接続
    し、前記チップ、前記ワイヤ、前記リードを樹脂被覆
    し、前記リードを前記樹脂の長さに切断し、前記チップ
    の裏面に位置するよう前記リード上の一部に半田ボール
    を形成したことを特徴とする半導体装置。
  2. 【請求項２】 前記起点が前記チップの端から９０μｍ
    〜１５０μｍ離れた前記リード上に位置する請求項１記
    載の半導体装置。
  3. 【請求項３】 前記ワイヤが前記起点から上に向かっ
    て、少なくとも前記チップの表面の高さに達するまで、
    ほぼ垂直に引き出されている請求項１記載の半導体装
    置。
  4. 【請求項４】 前記パッドの上にはあらかじめワイヤボ
    ンディングによる金ボ―ルが接着された請求項１記載の
    半導体装置。
  5. 【請求項５】 チップ・オン・リード構造のボール・グ
    リッド・アレイ型半導体装置の製造方法において、パッ
    ド上にワイヤボンディングによる金ボールを残留させる
    工程、チップ近傍のリード上の点を起点とし、前記パッ
    ド上の前記金ボールを終点として、リードとパッドとを
    ワイヤボンディングする工程、当該ワイヤボンディング
    によるワイヤ、当該チップ、当該リードを被覆すべく樹
    脂封止する工程、前記リードを樹脂封止された部分まで
    残すよう切断する工程、とからなることを特徴とする半
    導体装置の製造方法。
  6. 【請求項６】 前記ワイヤボンディングによるワイヤ
    が、前記リード上の起点から上方に向かって少なくとも
    前記チップの高さまで、ほぼ垂直に形成される請求項５
    記載の半導体装置の製造方法。
JP9256994A 1997-09-22 1997-09-22 半導体装置及びその製造方法 Expired - Fee Related JP2954109B2 (ja)

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JP9256994A JP2954109B2 (ja) 1997-09-22 1997-09-22 半導体装置及びその製造方法

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Application Number Priority Date Filing Date Title
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JPH1197476A true JPH1197476A (ja) 1999-04-09
JP2954109B2 JP2954109B2 (ja) 1999-09-27

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Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2007023852A1 (ja) * 2005-08-24 2007-03-01 Fujitsu Limited 半導体装置及びその製造方法
US7417324B2 (en) 2004-03-10 2008-08-26 Nec Electronics Corporation Semiconductor device and method for manufacturing the same

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7417324B2 (en) 2004-03-10 2008-08-26 Nec Electronics Corporation Semiconductor device and method for manufacturing the same
WO2007023852A1 (ja) * 2005-08-24 2007-03-01 Fujitsu Limited 半導体装置及びその製造方法
JP4998268B2 (ja) * 2005-08-24 2012-08-15 富士通セミコンダクター株式会社 半導体装置及びその製造方法
US8841776B2 (en) 2005-08-24 2014-09-23 Fujitsu Semiconductor Limited Stacked semiconductor chips having double adhesive insulating layer interposed therebetween

Also Published As

Publication number Publication date
JP2954109B2 (ja) 1999-09-27

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