JPH1187924A - Multilayered printed circuit board with non-penetrating via hole - Google Patents
Multilayered printed circuit board with non-penetrating via holeInfo
- Publication number
- JPH1187924A JPH1187924A JP24812097A JP24812097A JPH1187924A JP H1187924 A JPH1187924 A JP H1187924A JP 24812097 A JP24812097 A JP 24812097A JP 24812097 A JP24812097 A JP 24812097A JP H1187924 A JPH1187924 A JP H1187924A
- Authority
- JP
- Japan
- Prior art keywords
- via hole
- plating
- insulating resin
- layer
- interlayer insulating
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Abstract
Description
【０００１】[0001]
【発明の属する技術分野】本発明は、非貫通ビアホール
を有する多層プリント配線板に関する。The present invention relates to a multilayer printed wiring board having a non-penetrating via hole.
【０００２】[0002]
【従来の技術】多層プリント配線板に非貫通ビアホール
（以下、ビアホールという）を採用することは、配線設
計の自由度が増し、高密度配線への対応に適している。
高密度配線には、設計上ビアホールと該ビアホールの１
層外層側にあるビアホールが外層面から透視して重なる
ように配置する。これを実現するには、図２に示す構造
が開示されている。すなわちビアホールを有する多層プ
リント配線板の一例を断面で示したものである。該多層
プリント配線板の一般的な製造方法は、まず、内層回路
３を形成した基材２の表面に層間絶縁性樹脂４ａを形成
した後、レーザー又はプラズマアッシング若しくはフォ
トビアホールによりビアホール５を形成する。次に、ス
パッタリング又はめっきで層間絶縁性樹脂４ａの表面に
金属層を形成し、エッチングしてビアホール５の導電層
６ａ及び内層回路６ｂを得る。次に層間絶縁性樹脂４ｂ
を形成し、レーザーやプラズマアッシング若しくはフォ
トビアホールによりビアホール５と外層方向のほぼ同軸
上にビアホール７を形成する。この時、ビアホール５の
導電層６ａは露出している。次に、スパッタリング又は
めっきで層間絶縁性樹脂４ｂの表面に金属層を形成し、
エッチングしてビアホール７の導電層８ａ及び内層回路
８ｂを形成する。これを繰り返すことにより、ビアホー
ルを有する多層プリント配線板１を得る。しかし、この
構造によると外層側にあるビアホールの深さが増すた
め、ビアホールの導電層のつきまわりが悪くなったり、
ビアホール内への層間絶縁性樹脂の充填が困難となり表
面の平坦性が悪くなったりする。このような欠点を解決
する方法が特開平7−283538 号公報で開度されている。
その方法を図２を用いて説明する。ビアホール１３にア
ディティブ法でめっきして導電層１５ａ及び内層回路１
５ｂを形成した後、ビアホール１３に導電性又は非導電
性の充填材１６を充填する。次に、導電層１４ａ及び内
層回路１４ｂの表面にスパッタリング又はめっきにより
金属膜１７を形成する。これを繰り返すことにより多層
化している。また、これに類似した方法として、ビアホ
ール１３の導電層１５ａ及び内層回路１５ｂの形成をサ
ブトラクティブ法で行う方法がある。この場合、ビアホ
ール１３を形成した層間絶縁性樹脂12ａの表面にパネル
めっきを行い、ビアホール１３に充填材１６を充填す
る。次に充填材１６及びパネルめっき表面にスパッタリ
ング又はめっきにより金属膜１７を形成し、エッチング
によりビアホール１３の導電層１５ａ及び内層回路１５
ｂを形成する。2. Description of the Related Art The use of non-penetrating via holes (hereinafter referred to as "via holes") in a multilayer printed wiring board increases the freedom of wiring design and is suitable for high-density wiring.
In high-density wiring, a via hole and one of the via holes are designed by design.
The via holes on the outer layer side are arranged so as to be seen from the outer layer surface and overlap. To realize this, the structure shown in FIG. 2 is disclosed. That is, an example of a multilayer printed wiring board having a via hole is shown in cross section. In a general method of manufacturing the multilayer printed wiring board, first, an interlayer insulating resin 4a is formed on the surface of the substrate 2 on which the inner layer circuit 3 is formed, and then a via hole 5 is formed by laser, plasma ashing, or a photo via hole. . Next, a metal layer is formed on the surface of the interlayer insulating resin 4a by sputtering or plating and etched to obtain the conductive layer 6a of the via hole 5 and the inner layer circuit 6b. Next, interlayer insulating resin 4b
Is formed, and a via hole 7 is formed substantially coaxially with the via hole 5 in an outer layer direction by laser, plasma ashing, or a photo via hole. At this time, the conductive layer 6a of the via hole 5 is exposed. Next, a metal layer is formed on the surface of the interlayer insulating resin 4b by sputtering or plating,
The conductive layer 8a of the via hole 7 and the inner layer circuit 8b are formed by etching. By repeating this, multilayer printed wiring board 1 having via holes is obtained. However, according to this structure, since the depth of the via hole on the outer layer side is increased, the coverage of the conductive layer of the via hole is deteriorated,
It is difficult to fill the via hole with the interlayer insulating resin, and the flatness of the surface is deteriorated. A method for solving such a disadvantage is disclosed in Japanese Patent Application Laid-Open No. 7-283538.
The method will be described with reference to FIG. The conductive layer 15a and the inner layer circuit 1 are formed by plating the via hole 13 by an additive method.
After the formation of 5b, the via hole 13 is filled with a conductive or non-conductive filler 16. Next, a metal film 17 is formed on the surfaces of the conductive layer 14a and the inner layer circuit 14b by sputtering or plating. This is repeated to form a multilayer. As a similar method, there is a method of forming the conductive layer 15a of the via hole 13 and the inner layer circuit 15b by a subtractive method. In this case, the surface of the interlayer insulating resin 12a in which the via hole 13 is formed is subjected to panel plating, and the via hole 13 is filled with the filler 16. Next, a metal film 17 is formed on the filler 16 and the surface of the panel plating by sputtering or plating, and the conductive layer 15a of the via hole 13 and the inner layer circuit 15 are formed by etching.
b is formed.
【０００３】[0003]
【発明が解決しようとする課題】しかし、上記の方法で
は充填材１６を充填する工程と金属膜１７を形成する工
程が必要となる。また、金属膜１７の形成をめっきで行
う場合には、めっきの前処理の工程が必要となる上、充
填材１６との密着性を考慮しなくてはならない。金属膜
１７の形成をスパッタリングで行う場合には、永久レジ
スト１４に金属膜１７が形成しないようにするか、形成
した金属膜１７を取り除くことをしなければならない。
このように工程が長くなるため、歩留りの低下やコスト
が高くなるなどの欠点がある。また、サブトラクティブ
法で行う場合、パネルめっきの厚みに金属膜１７を加え
た厚みをエッチングして内層回路１５ｂを形成するため
挟ピッチ配線が不利となる。However, the above method requires a step of filling the filler 16 and a step of forming the metal film 17. Further, when the metal film 17 is formed by plating, a pretreatment step of plating is required, and the adhesion to the filler 16 must be taken into consideration. When the metal film 17 is formed by sputtering, it is necessary to prevent the metal film 17 from being formed on the permanent resist 14 or to remove the formed metal film 17.
Since the process is lengthened, there are disadvantages such as a decrease in yield and an increase in cost. In addition, in the case of performing the subtractive method, the thickness of the panel plating plus the metal film 17 is etched to form the inner layer circuit 15b.
【０００４】本発明の目的は、高密度化に対応できる多
層プリント配線板を歩留りが良く、低コストで提供する
ことにある。[0004] It is an object of the present invention to provide a multilayer printed wiring board capable of coping with high density at a high yield and at low cost.
【０００５】[0005]
【課題を解決するための手段】上記課題を解決するため
に、本発明では、図１に示すように、ビアホール２２は
層間絶縁性樹脂２１で充填されており、ビアホールめっ
き２３ａの外層側端面が層方向のほぼ同軸上の１層外側
にあるビアホール２４のビアホールめっき２５ａと直接
接続している。すなわち、ビアホールへの充填材は層間
絶縁性樹脂と同一樹脂であり、ビアホールへの充填は層
間絶縁性樹脂の形成と同時に成される。そのため、充填
材を必要とせず、充填する工程及び金属膜を形成する工
程も必要としない。In order to solve the above-mentioned problems, in the present invention, as shown in FIG. 1, a via hole 22 is filled with an interlayer insulating resin 21 and an outer layer side end face of a via hole plating 23a is formed. It is directly connected to the via-hole plating 25a of the via-hole 24 on the outer side of one layer substantially coaxially in the layer direction. That is, the filling material for the via hole is the same resin as the interlayer insulating resin, and the filling for the via hole is performed simultaneously with the formation of the interlayer insulating resin. Therefore, no filler is required, and neither a filling step nor a step of forming a metal film is required.
【０００６】また、ビアホールめっき２３ａとビアホー
ルめっき２５ａとが直接接続する構造であり、間に金属
膜等を介さないため接続信頼性にも優れている。また、
請求項２記載の発明では、図４に示すように、ビアホー
ル３０は層間絶縁性樹脂２９で充填されており、ビアホ
ールめっき３１ａの外層側端面３１ｃ及び内側面31ｄが
層方向のほぼ同軸上の１層外側にあるビアホール３２の
ビアホールめっき33ａと直接接続している。すなわち、
請求項１記載の発明と同様、ビアホールへの充填材は層
間絶縁性樹脂と同一樹脂であり、ビアホールへの充填は
層間絶縁性樹脂の形成と同時に成される。そのため、充
填材を必要とせず、充填する工程及び金属膜を形成する
工程も必要としない。また、ビアホールめっき３１ａの
外層側端面３１ｃから内側面３１ｄにかけてビアホール
めっき３３ａが直接接続しているため、より接続信頼性
を高めることができる。Further, the via hole plating 23a and the via hole plating 25a are directly connected to each other and have excellent connection reliability because no metal film or the like is interposed therebetween. Also,
According to the second aspect of the present invention, as shown in FIG. 4, the via hole 30 is filled with an interlayer insulating resin 29, and the outer side end face 31c and the inner side face 31d of the via hole plating 31a are substantially coaxial in the layer direction. It is directly connected to the via hole plating 33a of the via hole 32 located outside the layer. That is,
As in the first aspect of the present invention, the filling material for the via hole is the same resin as the interlayer insulating resin, and the filling for the via hole is performed simultaneously with the formation of the interlayer insulating resin. Therefore, no filler is required, and neither a filling step nor a step of forming a metal film is required. In addition, since the via-hole plating 33a is directly connected from the outer-side end surface 31c of the via-hole plating 31a to the inner side surface 31d, the connection reliability can be further improved.
【０００７】本発明により、高密度化に対応できる工程
が短縮できるため、歩留りが良く、低コスト多層プリン
ト配線板を提供することができる。According to the present invention, a process capable of coping with high density can be shortened, so that a yield can be improved and a low-cost multilayer printed wiring board can be provided.
【０００８】[0008]
〔実施例１〕本発明の具体的な実施例１について図５を
用いて説明する。まず、１８μｍ厚の銅箔３４ａと基材
３４ｂとからなる片面銅張りガラスエポキシ積層板３４
（日立化成工業社製；ＭＣＬ−Ｅ６７）を所要の大きさ
に裁断する（図５（ａ））。次に、所定のエッチングに
より内層回路３４ｃを形成し、３０℃の粗化液（硫酸５
ml／ｌ，過硫酸アンモニウム２００ｇ／ｌ）で２分間処
理して内層回路34ｃ表面に微細な凹凸を形成した。これ
を水洗後、７０℃の酸化膜形成液（リン酸三ナトリウム
３０ｇ／ｌ，過塩素酸ナトリウム１００ｇ／ｌ，水酸化
ナトリウム１２ｇ／ｌ）で５分間処理して前記凹凸面に
酸化膜を得た。[First Embodiment] A first embodiment of the present invention will be described with reference to FIG. First, a single-sided copper-clad glass epoxy laminate 34 composed of a copper foil 34a having a thickness of 18 μm and a base material 34b.
(MCL-E67, manufactured by Hitachi Chemical Co., Ltd.) is cut into a required size (FIG. 5A). Next, an inner layer circuit 34c is formed by predetermined etching, and a roughening solution (sulfuric acid 5
(ml / l, 200 g / l ammonium persulfate) for 2 minutes to form fine irregularities on the surface of the inner circuit 34c. This was washed with water and treated with an oxide film forming solution (trisodium phosphate 30 g / l, sodium perchlorate 100 g / l, sodium hydroxide 12 g / l) at 70 ° C. for 5 minutes to obtain an oxide film on the uneven surface. Was.
【０００９】次いで、水洗後、４５℃の還元液（ジメチ
ルアミノボラン１０ｇ／ｌ，水酸化ナトリウム１０ｇ／
ｌ）で１分間処理して、前記酸化膜を還元した後、水
洗，乾燥し酸化還元膜を得た（図５（ｂ））。Then, after washing with water, a reducing solution at 45 ° C. (dimethylaminoborane 10 g / l, sodium hydroxide 10 g /
1) for 1 minute to reduce the oxide film, followed by washing and drying to obtain a redox film (FIG. 5 (b)).
【００１０】[0010]
【表１】 [Table 1]
【００１１】次に、表１に示す絶縁性樹脂Ａを用い１５
本／cmのステンレスメッシュスクリーンで印刷塗工し、
８０℃の乾燥炉で３０分間乾燥して、厚さ約５０μｍの
層間絶縁性樹脂３５ａを得た（図５（ｃ））。次に、フ
ィルムマスクを層間絶縁性樹脂３５ａの表面に密着し、
超高圧水銀ランプで紫外線を７００ｍＪ／cm2 照射して
露光し、４０℃の現像液（炭酸ナトリウム；１０ｇ／
ｌ）を１.８kgf／cm2 の圧力で２分間スプレー処理し、
水洗後１５０℃の乾燥炉で３０分間硬化し外層側端部の
直径約１００μｍのビアホール３６を形成した（図５
（ｄ））。Next, using insulating resin A shown in Table 1
Book / cm stainless steel mesh screen
Drying was performed for 30 minutes in a drying oven at 80 ° C. to obtain an interlayer insulating resin 35a having a thickness of about 50 μm (FIG. 5C). Next, a film mask is brought into close contact with the surface of the interlayer insulating resin 35a,
Exposure was performed by irradiating an ultraviolet ray at 700 mJ / cm 2 with an ultra-high pressure mercury lamp, and a developing solution (sodium carbonate;
l) sprayed at a pressure of 1.8 kgf / cm 2 for 2 minutes,
After washing with water, the mixture was cured in a drying oven at 150 ° C. for 30 minutes to form a via hole 36 having a diameter of about 100 μm at the outer layer end (FIG. 5).
(D)).
【００１２】次に、層間絶縁性樹脂３５ａを粗化するた
めに８０℃、ｐＨ１４の過マンガン酸水溶液（過マンガ
ン酸カリウム６０ｇ／ｌ）で５分間処理し、水洗後４０
℃の中和液（硫酸ヒドロキシルアミン３０ｇ／ｌ）で５
分間処理した。さらに水洗後、めっき触媒液（日立化成
工業社製；HB101B）で５分間処理して、水洗後、活性化
液（日立化成工業社製；ADP601）で５分間処理した。次
いで水洗後、３８℃のフラッシュ銅めっき液（日立化成
工業社製；ＣＵＳＴ２０００）で３０分間処理して、
０.５μｍ 厚の銅めっき膜を全面に形成し、水洗，乾燥
した。続いて、電気銅めっき液(硫酸銅２００ｇ／ｌ，
硫酸１０ｇ／ｌ)で電流密度１.５Ａ／ｄｍ2，６０分間
銅めっきを行い、水洗後１７０℃の乾燥炉で４０分間硬
化し厚さ約２０μｍの銅めっき膜３７を得た（図５
（ｅ））。Next, in order to roughen the interlayer insulating resin 35a, it is treated with an aqueous solution of permanganic acid (potassium permanganate 60 g / l) at 80 ° C. and a pH of 5 for 5 minutes.
5 ° C with a neutralizing solution (hydroxylamine sulfate 30 g / l)
Minutes. After further washing with water, the plate was treated with a plating catalyst solution (HB101B, manufactured by Hitachi Chemical Co., Ltd.) for 5 minutes, and after washing with water, treated with an activating solution (ADP601, manufactured by Hitachi Chemical Co., Ltd.) for 5 minutes. Next, after washing with water, the plate was treated with a 38 ° C. flash copper plating solution (manufactured by Hitachi Chemical Co., Ltd .; CUST2000) for 30 minutes.
A copper plating film having a thickness of 0.5 μm was formed on the entire surface, washed with water and dried. Subsequently, an electrolytic copper plating solution (copper sulfate 200 g / l,
Copper plating was performed at a current density of 1.5 A / dm 2 for 60 minutes with sulfuric acid (10 g / l), washed with water and cured in a drying oven at 170 ° C. for 40 minutes to obtain a copper plating film 37 having a thickness of about 20 μm (FIG. 5).
(E)).
【００１３】次に、図５（ｂ）と同様の処理によりビア
ホールめっき３７ａ及び内層回路３７ｂを形成し、表面
に微細な凹凸を有する酸化還元膜を得た（図５
（ｆ））。次に、図５（ｃ）と同様の処理により層間絶
縁性樹脂３５ｂを形成すると同時にビアホール３６内に
層間絶縁性樹脂３５ｃを充填し、８０℃の乾燥炉で３０
分間乾燥した（図５（ｇ））。この時、層間絶縁性樹脂
３５ｂの厚さは、層間絶縁性樹脂３５ａの外層側端面か
ら約５０μｍであった。Next, a via-hole plating 37a and an inner layer circuit 37b are formed by the same processing as in FIG. 5B, and an oxidation-reduction film having fine irregularities on the surface is obtained (FIG. 5).
(F)). Next, the interlayer insulating resin 35b is formed by the same process as that shown in FIG. 5C, and at the same time, the interlayer insulating resin 35c is filled in the via hole 36, and then dried in an 80 ° C. drying oven.
After drying for minutes (FIG. 5 (g)). At this time, the thickness of the interlayer insulating resin 35b was about 50 μm from the outer layer end face of the interlayer insulating resin 35a.
【００１４】次に、図５(ｄ)と同様に露光，現像，硬化
し、ビアホール３６と外層方向のほぼ同軸上に外層側端
部の直径約１００μｍのビアホール３８を得た（図５
(ｈ)）。次に、図５（ｅ）と同様の処理により、厚さ約
２０μｍの銅めっき膜３９を得た（図５（ｉ））。次
に、図５（ｂ）と同様にエッチングによりビアホールめ
っき３９ａ及び外層回路３９ｂを得た（図５（ｊ））。
これにより、ビアホール３６の外層方向のほぼ同軸上に
ビアホール３８があり、かつビアホールめっき３７ａの
外層側端面とビアホールめっき３９ａが直接接続する多
層プリント配線板４０を得た。この多層プリント配線板
４０は、２６０℃のグリセリンに１分間の浸漬処理を１
０回繰り返しても、初期のビアホールシリーズ抵抗（穴
数１００個）の上昇率が１０％以内であった。Next, exposure, development, and curing are performed in the same manner as in FIG. 5D to obtain a via hole 38 having a diameter of about 100 μm at the outer layer side end substantially coaxially with the via hole 36 (FIG. 5).
(h)). Next, a copper plating film 39 having a thickness of about 20 μm was obtained by the same processing as in FIG. 5E (FIG. 5I). Next, via-hole plating 39a and outer layer circuit 39b were obtained by etching in the same manner as in FIG. 5B (FIG. 5J).
As a result, a multilayer printed wiring board 40 was obtained in which the via hole 38 was substantially coaxial with the via layer 36 in the outer layer direction, and the outer layer side end face of the via hole plating 37a was directly connected to the via hole plating 39a. This multilayer printed wiring board 40 is subjected to a 1 minute immersion treatment in glycerin at 260 ° C.
Even if it was repeated 0 times, the initial increase rate of the via-hole series resistance (100 holes) was within 10%.
【００１５】〔実施例２〕実施例２については、実施例
１のビアホール３８の形成で現像の時間を１５０秒に変
えて、ビアホールめっき３７ａの内側面がビアホール深
さ方向に約１０μｍほど露出するようにした。それ以外
の工程は実施例１に準じて行い、ビアホール３６の外層
方向のほぼ同軸上にビアホール３８があり、かつビアホ
ールめっき３７ａの外層側端面から内側面にかけてビア
ホールめっき３９ａが直接接続する多層プリント配線板
４０を得た。この多層プリント配線板４０に２６０℃の
グリセリンに１分間の浸漬処理を２０回繰り返しても、
初期のビアホールシリーズ抵抗（穴数１００個）の上昇
率が１０％以内であった。[Embodiment 2] In Embodiment 2, the inner side surface of the via hole plating 37a is exposed by about 10 μm in the via hole depth direction by changing the development time to 150 seconds in forming the via hole 38 of Embodiment 1. I did it. The other steps are performed in accordance with the first embodiment, and the multilayer printed wiring has the via hole 38 substantially coaxially in the outer layer direction of the via hole 36 and the via hole plating 39a directly connected from the outer layer end surface to the inner surface of the via hole plating 37a. A plate 40 was obtained. Even if this multilayer printed wiring board 40 is repeatedly immersed in glycerin at 260 ° C. for 1 minute 20 times,
The rise rate of the initial via hole series resistance (100 holes) was within 10%.
【００１６】〔実施例３〕実施例３については、実施例
１の方法に準じて内層回路３４ｃに黒化還元膜を形成す
るところまで行った。次に表１に示す絶縁性樹脂Ｂを用
い１５本／cmのステンレスメッシュスクリーンで印刷塗
工し、１７０℃の乾燥炉で９０分間乾燥して、厚さ約５
０μｍの層間絶縁性樹脂３５ａを得た。[Embodiment 3] In Embodiment 3, the process was performed up to the point where a blackening reduction film was formed in the inner circuit 34c according to the method of Embodiment 1. Next, using the insulating resin B shown in Table 1, a 15 mesh / cm stainless steel mesh screen was applied by printing and dried in a drying oven at 170 ° C. for 90 minutes to obtain a thickness of about 5 mm.
0 μm interlayer insulating resin 35a was obtained.
【００１７】次にメタルマスクを介して内層回路３４ｃ
が露出するようにエキシマレーザーのパルスを調整して
照射し、外層側端部の直径約１００μｍのビアホール３
６を形成した。次に、実施例１の方法に準じて層間絶縁
性樹脂３５ａの粗化からビアホールめっき３７ａ及び内
層回路３７ｂの酸化還元膜の形成までを行った。層間絶
縁性樹脂３５ａと同様に絶縁性樹脂Ｂを印刷塗工して、
層間絶縁性樹脂３５ｂを形成すると同時にビアホール３
６内に層間絶縁性樹脂３５ｃを充填し、１７０℃の乾燥
炉で９０分間乾燥した。この時、層間絶縁性樹脂３５ｂ
の厚さは、層間絶縁性樹脂３５ａの外層側端面から約５
０μｍであった。Next, an internal circuit 34c is inserted through a metal mask.
The excimer laser pulse is adjusted and irradiated so that the via hole 3 is exposed, and a via hole 3 having a diameter of about 100 μm at the outer layer end is formed.
6 was formed. Next, from the roughening of the interlayer insulating resin 35a to the formation of the via-hole plating 37a and the formation of the oxidation-reduction film of the inner layer circuit 37b, according to the method of the first embodiment. The insulating resin B is printed and coated in the same manner as the interlayer insulating resin 35a,
At the same time as forming the interlayer insulating resin 35b,
6 was filled with an interlayer insulating resin 35c and dried in a drying oven at 170 ° C. for 90 minutes. At this time, the interlayer insulating resin 35b
Is about 5 mm from the outer layer end face of the interlayer insulating resin 35a.
It was 0 μm.
【００１８】次に、メタルマスクを介してビアホールめ
っき３７ａの外層側端面が露出するようにエキシマレー
ザーのパルスを調整して照射し、外層側端部の直径約１
００μｍのビアホール３８を形成した。Next, a pulse of an excimer laser is adjusted and irradiated through a metal mask so that the outer layer end surface of the via hole plating 37a is exposed, and the outer layer side end has a diameter of about 1 mm.
A 00 μm via hole 38 was formed.
【００１９】次に、実施例１の方法に準じて粗化からビ
アホールめっき３９ａ及び外層回路３９ｂの形成まで行
った。これにより、ビアホール３６の外層方向のほぼ同
軸上にビアホール３８があり、かつビアホールめっき３
７ａの外層側端面とビアホールめっき３９ａが直接接続
する多層プリント配線板４０を得た。この多層プリント
配線板４０に２６０℃のグリセリンに１分間の浸漬処理
を１０回繰り返しても、初期のビアホールシリーズ抵抗
（穴数１００個）の上昇率が１０％以内であった。Next, the steps from roughening to formation of via-hole plating 39a and outer layer circuit 39b were performed in accordance with the method of the first embodiment. Thus, the via hole 38 is substantially coaxial with the via hole 36 in the outer layer direction, and the via hole plating 3
A multilayer printed wiring board 40 was obtained in which the outer-layer-side end face 7a was directly connected to the via-hole plating 39a. Even if this multilayer printed wiring board 40 was repeatedly immersed in glycerin at 260 ° C. for 1 minute ten times, the initial increase rate of the via-hole series resistance (100 holes) was within 10%.
【００２０】〔実施例４〕実施例４については、ビアホ
ール３６，３８の形成をプラズマアッシングを用いて行
った。それ以外の工程は実施例３に準じて行い、ビアホ
ール３６の外層方向のほぼ同軸上にビアホール３８があ
り、かつビアホールめっき３７ａの外層側端面とビアホ
ールめっき３９ａが直接接続する多層プリント配線板４
０を得た。この多層プリント配線板４０に２６０℃のグ
リセリンに１分間の浸漬処理を１０回繰り返しても、初
期のビアホールシリーズ抵抗（穴数１００個）の上昇率
が１０％以内であった。[Embodiment 4] In Embodiment 4, the via holes 36 and 38 were formed by using plasma ashing. Other steps are performed in accordance with the third embodiment. The multilayer printed wiring board 4 has a via hole 38 substantially coaxially in the outer layer direction of the via hole 36, and the outer layer end face of the via hole plating 37a is directly connected to the via hole plating 39a.
0 was obtained. Even if this multilayer printed wiring board 40 was repeatedly immersed in glycerin at 260 ° C. for 1 minute ten times, the initial increase rate of the via-hole series resistance (100 holes) was within 10%.
【００２１】〔実施例５〕実施例５については、実施例
３のビアホール３８の形成でエキシマレーザーのパルス
をビアホールめっき３７ａの内側面がビアホール深さ方
向に約１０μｍほど露出するように調整して照射した。
それ以外の工程は実施例３に準じて行い、ビアホール３
６の外層方向のほぼ同軸上にビアホール３８があり、か
つビアホールめっき３７ａの外層側端面から内側面にか
けてビアホールめっき３９ａが直接接続する多層プリン
ト配線板４０を得た。この多層プリント配線板４０に２
６０℃のグリセリンに１分間の浸漬処理を２０回繰り返
しても、初期のビアホールシリーズ抵抗（穴数１００
個）の上昇率が１０％以内であった。Fifth Embodiment In the fifth embodiment, the pulse of the excimer laser is adjusted so that the inner side surface of the via-hole plating 37a is exposed to about 10 μm in the via-hole depth direction by forming the via hole 38 in the third embodiment. Irradiated.
Other steps are performed according to the third embodiment, and the
A multilayer printed wiring board 40 having a via hole 38 substantially coaxially in the outer layer direction and directly connecting the via hole plating 39a from the outer layer end face to the inner side face of the via hole plating 37a was obtained. This multilayer printed wiring board 40
Even if the immersion treatment in glycerin at 60 ° C. for 1 minute is repeated 20 times, the initial via-hole series resistance (100 holes)
) Was within 10%.
【００２２】〔実施例６〕実施例６については、ビアホ
ール３６，３８の形成をプラズマアッシングを用いて行
った。それ以外の工程は実施例５に準じて行い、ビアホ
ール３６の外層方向のほぼ同軸上にビアホール３８があ
り、かつビアホールめっき３７ａの外層側端面から内側
面にかけてビアホールめっき３９ａが直接接続する多層
プリント配線板４０を得た。この多層プリント配線板４
０に２６０℃のグリセリンに１分間の浸漬処理を２０回
繰り返しても、初期のビアホールシリーズ抵抗（穴数１
００個）の上昇率が１０％以内であった。[Embodiment 6] In Embodiment 6, the via holes 36 and 38 were formed by using plasma ashing. Other steps are performed in accordance with the fifth embodiment. A multilayer printed wiring in which a via hole 38 is provided substantially coaxially in the outer layer direction of the via hole 36, and a via hole plating 39a is directly connected from the outer layer end surface to the inner surface of the via hole plating 37a. A plate 40 was obtained. This multilayer printed wiring board 4
Even if the immersion treatment in glycerin at 260 ° C. for 1 minute was repeated 20 times, the initial via hole series resistance (the number of holes was 1)
00) was within 10%.
【００２３】[0023]
【発明の効果】以上のように、ビアホールへの樹脂の充
填が層間絶縁性樹脂の形成と同時にできる上、外層方向
の同軸上に連なるビアホールの接続が直接できるため、
工程が短縮でき低コスト化が図れ、また歩留りも向上す
る。したがって、高密度配線に有利な非貫通ビアホール
を有する多層プリント配線板を高い生産性で得ることが
できる。As described above, the filling of the via holes with the resin can be performed simultaneously with the formation of the interlayer insulating resin, and the via holes connected coaxially in the outer layer direction can be directly connected.
The process can be shortened, the cost can be reduced, and the yield can be improved. Therefore, a multilayer printed wiring board having a non-through via hole advantageous for high-density wiring can be obtained with high productivity.
【図１】請求項１記載の発明を示す概略断面図である。FIG. 1 is a schematic sectional view showing the first embodiment of the present invention.
【図２】従来技術の非貫通ビアホールを有する多層プリ
ント配線板の概略断面図である。FIG. 2 is a schematic cross-sectional view of a multilayer printed wiring board having a non-through via hole according to the prior art.
【図３】従来技術の非貫通ビアホールを有する多層プリ
ント配線板の概略断面図である。FIG. 3 is a schematic sectional view of a multilayer printed wiring board having a non-penetrating via hole according to the prior art.
【図４】請求項２記載の発明を示す概略断面図である。FIG. 4 is a schematic sectional view showing the invention according to claim 2;
【図５】本発明を実施するための多層プリント配線板の
製造プロセスを示す概略断面図である。FIG. 5 is a schematic sectional view showing a manufacturing process of a multilayer printed wiring board for carrying out the present invention.
【符号の説明】 １，９，１８，２６，４０…多層プリント配線板、２，
１０，１９，２７，３４ｂ…基材、３，６ｂ，８ｂ，１
１，１５ｂ，２０，２３ｂ，２５ｂ，２８，３１ｂ，３
３ｂ，３４ｃ，３７ｂ…内層回路、４ａ，４ｂ，４ｃ，
１２ａ，12ｂ，１２ｃ，２１ａ，２１ｂ，２１ｃ，２
９，３５ａ，３５ｂ，３５ｃ…層間絶縁性樹脂、５，
７，１３，２２，２４，３０，３２，３６，３８…ビア
ホール、６ａ，８ａ，１５ａ…導電層、１４…永久レジ
スト、１６…充填材、１７…金属膜、２３ａ，２５ａ，
３１ａ，３３ａ，３７ａ，３９ａ…ビアホールめっき、
３１ｃ…外層側端面、３１ｄ…内側面、３４…片面銅張
りガラスエポキシ積層板、３４ａ…銅箔、３７，３９…
銅めっき膜、３９ｂ…外層回路。[Description of References] 1,9,18,26,40 ... multilayer printed wiring board, 2
10, 19, 27, 34b Base material, 3, 6b, 8b, 1
1, 15b, 20, 23b, 25b, 28, 31b, 3
3b, 34c, 37b ... inner layer circuits, 4a, 4b, 4c,
12a, 12b, 12c, 21a, 21b, 21c, 2
9, 35a, 35b, 35c ... interlayer insulating resin,
7, 13, 22, 24, 30, 32, 36, 38: via holes, 6a, 8a, 15a: conductive layer, 14: permanent resist, 16: filler, 17: metal film, 23a, 25a,
31a, 33a, 37a, 39a ... via-hole plating,
31c: outer layer side end face, 31d: inner side face, 34: single-sided copper-clad glass epoxy laminate, 34a: copper foil, 37, 39 ...
Copper plating film, 39b ... Outer layer circuit.
───────────────────────────────────────────────────── フロントページの続き (72)発明者 川本 峰雄 茨城県日立市大みか町七丁目１番１号 株 式会社日立製作所日立研究所内 (72)発明者 赤星 晴夫 茨城県日立市大みか町七丁目１番１号 株 式会社日立製作所日立研究所内 (72)発明者 宮崎 政志 神奈川県秦野市堀山下１番地 株式会社日 立製作所汎用コンピュータ事業部内 ──────────────────────────────────────────────────続 き Continuing from the front page (72) Mineo Kawamoto 7-1-1, Omika-cho, Hitachi City, Ibaraki Prefecture Inside Hitachi, Ltd. Hitachi Research Laboratory, Ltd. (72) Haruo Akahoshi 7-1-1, Omika-cho, Hitachi City, Ibaraki Prefecture No. 1 Hitachi, Ltd. Hitachi Research Laboratories (72) Inventor Masashi Miyazaki 1 Horiyamashita, Hadano-shi, Kanagawa Pref.
Claims (2)
線板において、層間絶縁性樹脂と同一の樹脂で充填され
た非貫通ビアホールのめっきの外層側端面と該ビアホー
ルの層方向のほぼ同軸上の１層外側にある非貫通ビアホ
ールのめっきとが直接接続しあうことを特徴とする多層
プリント配線板。1. A multilayer printed wiring board having a non-penetrating via hole, wherein an outer-layer-side end face of plating of the non-penetrating via hole filled with the same resin as an interlayer insulating resin and one layer substantially coaxial in a layer direction of the via hole. A multilayer printed wiring board characterized by being directly connected to plating of a non-through via hole on the outside.
線板において、層間絶縁性樹脂と同一の樹脂で充填され
た非貫通ビアホールのめっきの内側面から外層側端面に
かけて該ビアホールの層方向のほぼ同軸上の１層外側に
ある非貫通ビアホールのめっきとが直接接続しあうこと
を特徴とする多層プリント配線板。2. A multilayer printed wiring board having a non-penetrating via hole, wherein the non-penetrating via hole filled with the same resin as the interlayer insulating resin is substantially coaxial in the layer direction of the via hole from the inner side surface to the outer layer side end surface. Wherein the plating of the non-penetrating via hole on the outside of one layer is directly connected to each other.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP24812097A JPH1187924A (en) | 1997-09-12 | 1997-09-12 | Multilayered printed circuit board with non-penetrating via hole |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP24812097A JPH1187924A (en) | 1997-09-12 | 1997-09-12 | Multilayered printed circuit board with non-penetrating via hole |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH1187924A true JPH1187924A (en) | 1999-03-30 |
Family
ID=17173535
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP24812097A Pending JPH1187924A (en) | 1997-09-12 | 1997-09-12 | Multilayered printed circuit board with non-penetrating via hole |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH1187924A (en) |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2003023253A (en) * | 2001-07-10 | 2003-01-24 | Ibiden Co Ltd | Multilayered printed wiring board |
| CN1302693C (en) * | 2002-12-12 | 2007-02-28 | 三星电机株式会社 | Combined printed circuit board with superposed through holes and producing method thereof |
| US8030579B2 (en) | 2001-03-14 | 2011-10-04 | Ibiden Co., Ltd. | Multilayer printed wiring board |
| US11552037B2 (en) | 2020-07-28 | 2023-01-10 | Samsung Electronics Co., Ltd. | Semiconductor package |
-
1997
- 1997-09-12 JP JP24812097A patent/JPH1187924A/en active Pending
Cited By (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US8030579B2 (en) | 2001-03-14 | 2011-10-04 | Ibiden Co., Ltd. | Multilayer printed wiring board |
| US8324512B2 (en) | 2001-03-14 | 2012-12-04 | Ibiden Co., Ltd. | Multilayer printed wiring board |
| US9040843B2 (en) | 2001-03-14 | 2015-05-26 | Ibiden Co., Ltd. | Multilayer printed wiring board |
| JP2003023253A (en) * | 2001-07-10 | 2003-01-24 | Ibiden Co Ltd | Multilayered printed wiring board |
| CN1302693C (en) * | 2002-12-12 | 2007-02-28 | 三星电机株式会社 | Combined printed circuit board with superposed through holes and producing method thereof |
| US11552037B2 (en) | 2020-07-28 | 2023-01-10 | Samsung Electronics Co., Ltd. | Semiconductor package |
| US11862596B2 (en) | 2020-07-28 | 2024-01-02 | Samsung Electronics Co., Ltd. | Semiconductor package |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| JP2000188479A (en) | Multilayer printed wiring board | |
| JP3012590B2 (en) | Method for manufacturing multilayer printed wiring board | |
| JPH1187924A (en) | Multilayered printed circuit board with non-penetrating via hole | |
| JPH10322024A (en) | Built-up multilayered printed wiring board having nonthrough via hole, and its manufacture | |
| JP3500977B2 (en) | Manufacturing method of double-sided circuit board | |
| JP2699920B2 (en) | Method for manufacturing multilayer printed wiring board | |
| JP4862682B2 (en) | Printed wiring board and manufacturing method thereof | |
| JP2001015928A (en) | Multilayer printed wiring board and its manufacture | |
| JPH1187910A (en) | Printed wiring board and manufacture therefor | |
| JP2003115662A (en) | Method of manufacturing semiconductor device substrate | |
| JP6598694B2 (en) | Thick copper circuit board and manufacturing method thereof | |
| JP2000261149A (en) | Mutilayer printed wiring board and manufacture thereof | |
| JP2000091742A (en) | Method for manufacturing printed-wiring board | |
| JP2001177248A (en) | Wiring board, manufacturing method therefor, and electronic apparatus | |
| JP2016127251A (en) | Printed-circuit board and method for manufacturing the same | |
| JP2944576B2 (en) | Manufacturing method of multilayer printed wiring board | |
| JPH10224036A (en) | Build-up printed wiring board and its manufacturing method | |
| JP2001196745A (en) | Multilayer printed wiring substrate | |
| JPH08204339A (en) | Manufacture of printed wiring board | |
| JP2000151100A (en) | Manufacture of printed wiring board | |
| JPH07297547A (en) | Manufacture of multilayer printed wiring board | |
| JPH1140951A (en) | Manufacture of multilayred wiring board | |
| JPH11261220A (en) | Manufacture of multilayered printed wiring board | |
| JPH10190233A (en) | Manufacture of multilayer interconnection board | |
| TW478305B (en) | Multi-layer substrate manufacturing method |