TW478305B - Multi-layer substrate manufacturing method - Google Patents

Abstract

There is provided a multi-layer substrate manufacturing method, which comprises the steps of: (a) providing an interlayer circuit board formed thereon a conductive circuit; (b) forming a dielectric layer on the interlayer circuit board; (c) drilling the dielectric layer at a specific position by machine or laser until reaching the conductive circuit, thereby forming a blind-via; (d) electrolessly plating a conductive layer on the surface of the dielectric layer and blind-via; (e) forming an anti-etchant on the conductive layer, and selectively etching the conductive layer to form an external conductive circuit; and (f) removing the anti-etchant. Because no photosensitive polymer technology is not required to form the blind-via in the multi-layer substrate manufacturing method of the present invention, it is able to simplify the manufacturing process and increase the efficiency. In addition, because the mechanical or laser drill is provided with a better accuracy, the precision of the hole position for the formed blind-via is high.

Description

478305 五、發明說明α) 發明領域： 本發明係有關於一種基板製程，特別有關於一種利用增 層法(b u i 1 d - u ρ )的多層基板製程。 先前技術： y 目 '前用來製造务層基板的的增層法技術主要包含自限式 雷身ί 鑽孑L (conformal mask self — limited drilling)〉去以· 及光成像導孔（p h o t ο - v i a )法。/ 第一至五圖係用以說明利用自限式雷射鑽孔法製造多層 基板之主要製程步驟。第一圖揭示一夾層電路板 (interlayer circuit board)100，其上具有、兩層導電電 路。參照第二圖，兩背膠銅箔（resin coated copper， RCC ) 1 1 0係以習用之方法（例如熱壓合法）層壓 (laminating)於該夾層電路板100之上下兩面。該背膠銅 羯1 1 0係包含一絕緣樹脂層1 1 0 a以及一銅層1 1 0 b。參照第 三圖，光阻層1 2 0係利用習知技術及材料塗覆在層壓於夾 層電路板1 0 0上之銅層1 1 0 b，然後成像（i m a g i n g )以及il影 (d e v e 1 o p i n g )。如眾所週知，一光罩被用來使該光阻層只 在特定區域成像，而在顯影後該特定區域之光阻會被移 除，使得該銅層1 1 0 b之預先設定部分裸露於該光阻層。然 後該銅層1 1 0 b的裸露部分會被蝕刻而在預先設定位置形成 細孔（f i n e h ο 1 e s )。參照第四圖，將該剩餘之光阻移除 後，對裸露於銅層1 1 〇 b細孔内之絕緣樹脂層1 1 0 a施以覆數 個雷射脈衝雷射光束而藉此形成盲孔（b 1 i n d - v i a )，其中 該每一雷射脈衝係大於絕緣樹脂層1 1 0 a之燒融閥值478305 V. Description of the invention α) Field of the invention: The present invention relates to a substrate manufacturing process, and more particularly to a multilayer substrate manufacturing process using a build-up method (b u i 1 d-u ρ). Prior technology: The technology of the build-up method used to manufacture the substrate of the current layer mainly includes a self-limiting drill body L (conformal mask self — limited drilling)> and a light imaging guide hole (phot ο -via) method. / The first to fifth figures are used to illustrate the main process steps of manufacturing multilayer substrates by using the self-limiting laser drilling method. The first figure discloses an interlayer circuit board 100 having two layers of conductive circuits thereon. Referring to the second figure, two resin-coated copper foils (RCC) 1 1 0 are laminated on the upper and lower sides of the sandwich circuit board 100 by a conventional method (for example, hot pressing). The adhesive-backed copper alloy 1 1 0 includes an insulating resin layer 1 1 0 a and a copper layer 1 1 0 b. Referring to the third figure, the photoresist layer 1 2 0 is a copper layer 1 1 0 b laminated on a sandwich circuit board 1 0 0 using conventional techniques and materials, and then imaging and devel 1 oping). As is well known, a photomask is used to make the photoresist layer image only in a specific area, and the photoresist in the specific area will be removed after development, so that a predetermined part of the copper layer 1 1 0 b is exposed in the Photoresist layer. Then, the exposed portion of the copper layer 1 1 0 b is etched to form fine holes (f i n e h ο 1 e s) at a predetermined position. Referring to the fourth figure, after removing the remaining photoresist, the insulating resin layer 1 1 0 a exposed in the pores of the copper layer 1 1 0b was covered with several laser pulse laser beams to form Blind hole (b 1 ind-via), where each laser pulse is greater than the melting threshold of the insulating resin layer 1 1 0 a

P00-103.ptd 第4頁 478305 五、發明說明（2) (ablation threshold) 但 A会π Μ 於鋼層11 〇b之燒融閥值。然 後’參知、弟五圖’將銅層13◦鍍在全部的表面區域（包括 苜孔），错此電性連接該夾層電路板100之導電電路以及 銅層I10b，其一般係利用,無電極電鍍銅（eiectr〇iess = Platlng)技術。該銅層13〇可在夹層電路板丨⑽之 辱-电電路、盲孔以及銅層11 〇b間建立電性連接。最後，形 成一抗蝕刻劑於該銅層130上’然後選擇性蝕刻該銅層13〇 以形成外導電電路（未示於圖中）。 第六至十圖係用以說明利用光成像導孔法製造多層基板 之主要製程步驟。第六圖揭示一感光介質（ph〇t〇imagable d 1 e 1 e c t r 1 c，_ P I D ) 2 1 0利用習知技術塗覆在夾層電路板丨〇 〇 上。然後對該感光介質2 1 0成像以及顯影而形成感光盲孔 (Photo V1 a) 2 l〇a (參見第七圖）。接著，利用機械鑽孔 或雷射鑽孔形成通孔（1：11]：〇1^11-11〇16)220 (參見第八圖 )。參照第九圖，將銅層2 3 0鍍在全部的表面區域（包括 感光目孔以及通孔）。隶後，形成一抗餘刻劑於該導電層 上’然後選擇性蝕刻該導電層以形成外導電電路（未〜示^ 圖中）。 、 削返增層法技術在形成盲孔時皆需使用成像（i m a g丨n g ) 以及顯影（devel oping)技術，因此會有因成像、顯影的誤 差而導致孔位偏移的問題。 本發明因此提供一種多層基板製造方法，其可克服或至 少改善前述之先前技術的問題。 發明概要： 、P00-103.ptd Page 4 478305 V. Description of the invention (2) (ablation threshold) But A will be π Μ at the melting threshold of steel layer 11 〇b. Then "Refer to the picture of the younger brother and the younger brother" to plate the copper layer 13◦ on all surface areas (including the alfalfa hole), and electrically connect the conductive circuit of the sandwich circuit board 100 and the copper layer I10b. It is generally used. Electroplated copper (eiectróiess = Platlng) technology. The copper layer 130 can establish an electrical connection between a sandwich circuit board, an electrical circuit, a blind hole, and the copper layer 110b. Finally, an anti-etching agent is formed on the copper layer 130 and then the copper layer 13 is selectively etched to form an external conductive circuit (not shown in the figure). The sixth to tenth diagrams are used to explain the main process steps of manufacturing a multi-layer substrate by the photo-imaging via method. The sixth figure reveals a photosensitive medium (ph0tomagically d 1 e 1 e c t r 1 c, _ P I D) 2 1 0 coated on a sandwich circuit board using a conventional technique. Then, the photosensitive medium 2 10 is imaged and developed to form a photosensitive blind hole (Photo V1 a) 2 10a (see the seventh figure). Next, a through-hole (1:11]: 〇1 ^ 11-11〇16) 220 is formed by mechanical drilling or laser drilling (see the eighth figure). Referring to the ninth figure, the copper layer 230 is plated on the entire surface area (including the photosensitive hole and the through hole). After that, an anti-residue agent is formed on the conductive layer, and then the conductive layer is selectively etched to form an external conductive circuit (not shown in the figure). In the formation of the blind hole, both the cutting and increasing layer technology need to use imaging (imaging) and developing (devel oping) technology, so there will be a problem of hole displacement due to errors in imaging and development. The present invention therefore provides a multilayer substrate manufacturing method that can overcome or at least improve the aforementioned problems of the prior art. Summary of the invention:

P00-103.ptd 第5頁 478305 五、發明說明（3) 本發明之主要目的係提供一種多層基板製造方法，其係 鑽孔的方式直接形成盲孔，藉此簡化製程， 技術因成像、顯影的誤差而導致孔位偏移的 以機械或雷射 並且改善先前 問題。 根據本發明 (a ) 提供一夾 上具有導電電 C c ) 在該介電 盲孑L ( b 1 i n d — v plating) — 導 一抗触 成外導 由於 之孔位 法在形 製程， 為了 顯特徵 作詳細 發明說 第十 之主要 第十 中，該 刻劑於 電電路 機械或 精確度 成盲孔 提高效 讓本發 ，下文 說明如 明： 圖至第 製程步 圖揭不 夾層電 之多層基板製造方法， 層電路板（interlayer 路；（b )形成一介電層 層特定位置鑽孔直至該 i a ) ; ( d) 無電極電鍍（ 電層於該介電層以及盲 該導電層上，然後選擇 ;及（f ) 移除該抗蝕刻 雷射鑽孔之精確度較佳 較高。此外，由於本發 時不需使用成像以及顯 率。 明之上述和其他目的、 特舉本發明較佳實施例 下。 其包含下列步驟： circuit board)，其 於該夾層電路板上； 導電電路，用以形成 electroless ly 孔之表面；（e ) 形成 性钱刻該導電層以形 劑。 ，因此其所形成盲孔 明之多層基板製造方 影技術，因此可簡化 特徵、和優點能更明 ，並配合所附圖示， « 圖係用以說明本發明多層基板製造方法 驟 一夾層電路板10 0。雖然在本較佳實施例 路板具有兩層導電電路；然而必要的話，用P00-103.ptd Page 5 478305 V. Description of the invention (3) The main purpose of the present invention is to provide a multilayer substrate manufacturing method, which directly forms blind holes by drilling, thereby simplifying the manufacturing process. The error caused the displacement of the hole by mechanical or laser and improved the previous problem. According to the present invention (a), a clip is provided with conductive electricity C c) in the dielectric blind 孑 L (b 1 ind — v plating) — conductive primary contact to external conductive due to the hole location method in the forming process, in order to show Features The invention is described in detail in the tenth main tenth, the engraving is a blind hole in the electrical circuit mechanical or accuracy to improve the efficiency, the following description is as clear as: Figure to the first step of the process to reveal the multilayer substrate without interlayer electricity Manufacturing method, layer circuit board (interlayer circuit; (b) forming a dielectric layer layer at a specific position and drilling to the ia); (d) electrodeless plating (electrical layer on the dielectric layer and blind conductive layer, and then Choose; and (f) the accuracy of removing the anti-etching laser drilling is better. In addition, since imaging and visibility are not required at the time of the present invention, the above-mentioned and other purposes are mentioned, and the preferred implementation of the present invention is enumerated. It includes the following steps: a circuit board) on the interlayer circuit board; a conductive circuit for forming the surface of an electrolessly hole; (e) a conductive layer engraved with a forming agent. Therefore, the blind hole formation of the multi-layer substrate manufacturing square shadow technology can simplify the features and advantages, and cooperate with the attached drawings. «The diagram is used to explain the multilayer substrate manufacturing method of the present invention. A sandwich circuit board 10 0. Although the circuit board in this preferred embodiment has two layers of conductive circuits; however, if necessary,

P00-103.ptd 第6頁 478305 五、發明說明（4) 於本發明之夾層電路板可从只包含一層導電電路。可以理 解的是，該夹層電路板1 0 0亦可以是利用任一種增層法 (build-up)製程技術形y成的多層板。該夾層電路板1 〇〇 可由破璃纖維強化BT (bismaleimide-triazine)樹脂，或 FR-4坡璃纖維強化環氧樹脂（fiberglass reinforced e p o x y r e s i η )製成之蕊層（c 〇 r e 1 a y e r )形成，藉此增加該 多層基板之機械強度。 參照第十一圖，一介電層3丨〇利用習知技術（例如網板P00-103.ptd Page 6 478305 V. Description of the Invention (4) The sandwich circuit board of the present invention may include only one layer of conductive circuit. It can be understood that the interlayer circuit board 100 may also be a multi-layer board formed by using any build-up process technology. The sandwich circuit board 100 may be formed of a bismaleimide-triazine (BT) resin, or a core layer (c ore 1 ayer) made of FR-4 fiberglass reinforced epoxy resin (fibreglass reinforced epoxyresi η). , Thereby increasing the mechanical strength of the multilayer substrate. Referring to the eleventh figure, a dielectric layer 3 丨 〇 uses a conventional technology (such as a screen

印刷（s c r e e n p r i η 1: i n g)、旋轉塗佈（s p i n c 〇 a 1: i n g )、或 是噴灑塗佈（spray coating))塗、覆在夹層電路板loo上 該介電層3 1 0較佳為熱固性樹脂。 -. 麥照第十二圖，在該介電層3丨〇特定位置鑽孔直至該夹 層電路板100之導電電路，用以形成盲孔 ^ —V1,a)31〇a，並且裸露該導電電路之部分。該鑽孔 ί射鑽孔或雷射鑽孔的方式達成，其較佳係利用 束係用來^ ^ i因為其精準度高。可以理解的是，雷射光 板1〇〇之導带；|電層310之特定位置直到露出該夹層::電路Printing (screenpri η 1: ing), spin coating (spinc 〇a 1: ing), or spray coating (spray coating) coating, coating on the interlayer circuit board loosing the dielectric layer 3 1 0 is better It is a thermosetting resin. -. Mai according to the twelfth figure, drill a hole at a specific position of the dielectric layer 3 丨 up to the conductive circuit of the sandwich circuit board 100 to form a blind hole ^ -V1, a) 31〇a, and expose the Part of a conductive circuit. The method of drilling or laser drilling is achieved, and it is better to use the beam system ^ ^ i because of its high accuracy. It can be understood that the conduction band of the laser light plate 100; the specific position of the electrical layer 310 until the interlayer is exposed :: circuit

(未示於圖:、虬或雷射鑽孔形成通孔（through-hole) 雷射、鏡鋁石i。適合於該步驟之當射類型包含二氧化碳 射、準分子泰田石（yttriUm aluminum garnet， YAG)雷 化碳雷射，;= 等，其中較佳使用二氧 度必須加以批二"率冋。可以理解的是，該介電層之厚 i制。因為如果介電層太厚，則要在合理的時(Not shown in figure: 虬, 虬, or laser drilling through-hole to form a through-hole laser, mirror alumina i. Suitable types for this step include carbon dioxide, excimer Taitian stone (yttriUm aluminum garnet) , YAG) laser carbon laser,; = etc. Among them, it is better to use the dioxin, which must be approved by the second rate. It is understandable that the thickness of the dielectric layer is made. Because if the dielectric layer is too thick, , Then at a reasonable time

P00-103.ptd 第7頁 ^305 五、發明說明（5) 間内，以足夠能量、 電電路將會相當田.射元成鑽孔而又不穿透盲孔下的導 之厚度應小於3密爾、Γ。·為達到合理的生產速率，該介電層 熱固性樹脂介電材料丨）車乂佺小於2密爾（m 1 1 )(當使用 足以在不同層的導電I^。1外，該介電層之最小厚度應 參昭第十二n ^ =电路之間建立電氣絕緣。 …、乐卞一圖，在該介雷#3 亡 上—金屬層例如鋼居3 ," 目孔3 10a之表面鍍 板鍍通孔常用之#; 。本步騍之電鍍可利用印刷電路 ⑶咖Plating))達成。特別言之~e^et^iess :及盲孔之表面與欲作為鍍核(nucl⑼：J、=將該介電層 貝C例如鈀）接觸，然後再與無電 a 1 η§)之物 極鋼浴⑷ ectWess copper bath))^觸^無電 以及整個盲孔表面係為該鍍層金屬覆蓋。該鍍声氣層 即鋼層3 2 0 ,係用以在夾層電路板丨〇 〇之導帝=二五㈣，亦 之間建立電性連接。 夺屯电路以及盲孔 $著’利用一熱滾層壓機（h〇t-roll laminat〇〇 2劑（例如感光乾mPh〇t〇sens⑴ve dry fUm)) >P00-103.ptd Page 7 ^ 305 V. Description of the invention (5) Within a period of time, with sufficient energy, the electric circuit will be quite field-oriented. The thickness of the guide element drilled without penetrating the blind hole should be less than 3 mil, Γ. In order to achieve a reasonable production rate, the dielectric layer thermosetting resin dielectric material is less than 2 mils (m 1 1) (when using enough conductive I ^ in different layers. 1 outside, the dielectric layer The minimum thickness should refer to the twelfth figure n ^ = Electrical insulation is established between the circuits... The plated plated through-holes are commonly used. The electroplating in this step can be achieved using printed circuits (plating). In particular, ~ e ^ et ^ iess: and the surface of the blind hole is in contact with the object to be plated (nucl⑼: J, = the dielectric layer C, such as palladium), and then is contacted with the non-electrical a 1 η§. Steel bath (ectWess copper bath)) ^ contact ^ no electricity and the entire blind hole surface is covered by the plating metal. The sound plating gas layer, that is, the steel layer 3 2 0, is used to establish an electrical connection between the conductor of the sandwich circuit board = two or five. Wintun circuit and blind hole $ 着 ’using a hot roll laminator (h〇t-roll laminat〇2 agent (such as photosensitive dry mPh〇tsensensenve dry fUm)) >

成在外側銅層3 2 0上，然後選擇性蝕刻該導兩爲、，/ is m 1包尽以形成々V i:ί路（未示於圖中）。最I，將抗蝕刻劑移除後，即 可‘得四層的多層基板。 Ρ 由於機械或雷射鑽孔之精確度較佳，因此Α ^上 ， /、尸7 成 〜孔位精確度較高。因此本發明之多層基板製造方去α 幅改善先前技術因成像、顯影的誤差而導致丨 可大 通。而由於本發明之多層基板製造方法在形点亡 〇1 乃又目札日守不需Formed on the outer copper layer 3 2 0, and then selectively etched the two leads to form a 々V i: ί road (not shown in the figure). First, after removing the etching resist, a four-layer multilayer substrate can be obtained.由于 Because the accuracy of mechanical or laser drilling is better, the accuracy of the hole position and the position of the hole is higher. Therefore, the multi-layer substrate manufacturing method of the present invention can reduce the alpha frame to improve the prior art due to the errors in imaging and development. However, because the multilayer substrate manufacturing method of the present invention is dead in shape, it is unnecessary

478305 五、發明說明（6) 使用成像以及顯影技術，因此可簡化製程，提高效率。此 外，因為雷射鑽孔或機械鑽孔在形成盲孔時沒有使用有機 化學品或有機溶液，因此其要比習知技術使用的感光聚合 物技術更為環保。 雖然本發明已以前述較佳實施例揭示，然其並非用以限 定本發明，任何熟習此技藝者，在不脫離本發明之精神和 範圍内，當可作各種之更動與修改，因此本發明之保護範 圍當視後附之申請專利範圍所界定者為準。478305 V. Description of the invention (6) The use of imaging and development technology can simplify the process and improve efficiency. In addition, because laser or mechanical drilling does not use organic chemicals or organic solutions when forming blind holes, it is more environmentally friendly than the photopolymer technology used in conventional technologies. Although the present invention has been disclosed by the aforementioned preferred embodiments, it is not intended to limit the present invention. Any person skilled in the art can make various changes and modifications without departing from the spirit and scope of the present invention. The scope of protection shall be determined by the scope of the attached patent application.

P00-103.ptd 第9頁 478305 圖式簡單說明 圖示說明： 第1圖至第5圖：係用以說明利用習知的自限式雷射鑽孔 法製造多層基板之主要製程步驟； 第6圖至第9圖：係用以說明利用習知的光成像導孔法製 造多層基板之主要製程步驟；及 第1 0圖至第1 3圖：係用以說明根據本發明較佳實施例之 多層基板製造方法。 圖號說明 100 銲 引 線 形 式晶 片封裝構造 100 夾 層 電 路 板 < 110 背 膠 銅羯 1 10a 樹 脂 層 110b 銅 層 120 光 阻 層 130 銅 層 210 感 光 介 質 210a 感 光 盲孑L 220 通 孔 230 銅 層 310 介 電 層 310a 盲 孔 320 銅 層 # «P00-103.ptd Page 9 478305 The diagram is briefly explained and illustrated: Figures 1 to 5 are used to explain the main process steps of manufacturing multilayer substrates by the conventional self-limiting laser drilling method; Figures 6 to 9 are used to explain the main process steps of manufacturing a multilayer substrate by the conventional photoimaging via method; and Figures 10 to 13 are used to illustrate the preferred embodiment according to the present invention Multilayer substrate manufacturing method. Description of Drawing Numbers 100 Welding lead form chip package structure 100 Sandwich circuit board < 110 Adhesive-backed copper 1 10a Resin layer 110b Copper layer 120 Photoresist layer 130 Copper layer 210 Photosensitive medium 210a Photosensitive blind L 220 through hole 230 Copper layer 310 Dielectric layer 310a blind hole 320 copper layer # «

P00-103.ptd 第10頁P00-103.ptd Page 10

Claims (1)

478305 s、申請專利範圍 1、 一種多層基板製造方法，其包含下列步驟： 提供一夹層電路板（interlayer circuit board)，其上 具有導電電路； 形成一介電層於該夾層電路板上； 在該介電層特定位置鑽孔直至該導電電路，用以形成盲 孑 L ( b 1 i ΙΊ d — v i a )： 無電極電鐘（electrolessly plating) —導電層於該介 電層以及盲孔之表面； 形成一抗蝕刻劑於該導電層上，然後選擇性蝕刻該導電 層以形成外導電電路；及 移除該抗触刻劑。 < 2、 依申請專利範圍第1項之多層基板製造方法，其中該夾 層電路板具有一層導電電路形成於該夾層電路板的一面。 3、 依申請專利範圍第1項之多層基板製造方法，其中該夾 層電路板具有兩層導電電路分別形成於該夾層電路板的爾 :,fr· 面0 —— 4、 依申請專利範圍第1項之多層基板製造方法，其中在該 介電層特定位置鑽孔之步驟係利用機械鑽孔法達成。 5、 依申請專利範圍第1項之多層基板製造方法，其中在介 電層特定位置鑽孔之步驟係利用雷射鑽孔法達成。478305 s, patent application scope 1, a method for manufacturing a multilayer substrate, comprising the following steps: providing an interlayer circuit board with conductive circuits thereon; forming a dielectric layer on the interlayer circuit board; The dielectric layer is drilled at a specific position up to the conductive circuit to form a blind electrode L (b 1 i Ι Ί d — via): Electrolessly plating — a conductive layer is on the surface of the dielectric layer and the blind hole Forming an anti-etching agent on the conductive layer, and then selectively etching the conductive layer to form an external conductive circuit; and removing the anti-etching agent. < 2. The method for manufacturing a multi-layer substrate according to item 1 of the application, wherein the sandwich circuit board has a layer of conductive circuits formed on one side of the sandwich circuit board. 3. The multilayer substrate manufacturing method according to item 1 of the scope of patent application, wherein the sandwich circuit board has two layers of conductive circuits formed on the sandwich circuit board, respectively: fr · face 0 —— 4, according to the first scope of the patent application The multilayer substrate manufacturing method of this item, wherein the step of drilling a hole in a specific position of the dielectric layer is achieved by a mechanical drilling method. 5. The method for manufacturing a multilayer substrate according to item 1 of the scope of patent application, wherein the step of drilling a hole in a specific position of the dielectric layer is achieved by a laser drilling method. P00-103.ptd 第11頁 478305 六、申請專利範圍 6、 依申請專利範圍第1項之多層基板製造方法，其中該介 電層為熱固性樹脂。 7、 依申請專利範圍第1項之多層基板製造方法，其中該夾 層電路板係以玻璃纖維強化B T ( b i s m a 1 e i m i d e - t r i a z i n e ) 樹脂形成。 8、 依申請專利範圍第1項之多層基板製造方法，其中該夾 層電路板係以F R - 4玻璃纖維強化環氧樹脂形成。 «P00-103.ptd Page 11 478305 6. Scope of patent application 6. The method for manufacturing a multilayer substrate according to item 1 of the scope of patent application, wherein the dielectric layer is a thermosetting resin. 7. The method for manufacturing a multilayer substrate according to item 1 of the scope of the patent application, wherein the sandwich circuit board is formed of glass fiber reinforced B T (b i s m a 1 e i m i d e-t r i a z i n e) resin. 8. The method for manufacturing a multilayer substrate according to item 1 of the scope of the patent application, wherein the sandwich circuit board is formed of F R-4 glass fiber reinforced epoxy resin. « P00-103.ptd 第12頁P00-103.ptd Page 12