JP2699920B2 - Method for manufacturing multilayer printed wiring board - Google Patents
Method for manufacturing multilayer printed wiring boardInfo
- Publication number
- JP2699920B2 JP2699920B2 JP9016295A JP9016295A JP2699920B2 JP 2699920 B2 JP2699920 B2 JP 2699920B2 JP 9016295 A JP9016295 A JP 9016295A JP 9016295 A JP9016295 A JP 9016295A JP 2699920 B2 JP2699920 B2 JP 2699920B2
- Authority
- JP
- Japan
- Prior art keywords
- insulating layer
- forming
- via hole
- layer
- printed wiring
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
Classifications
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/0011—Working of insulating substrates or insulating layers
- H05K3/0017—Etching of the substrate by chemical or physical means
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/10—Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern
- H05K3/18—Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern using precipitation techniques to apply the conductive material
- H05K3/181—Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern using precipitation techniques to apply the conductive material by electroless plating
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/38—Improvement of the adhesion between the insulating substrate and the metal
- H05K3/382—Improvement of the adhesion between the insulating substrate and the metal by special treatment of the metal
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/40—Forming printed elements for providing electric connections to or between printed circuits
- H05K3/4038—Through-connections; Vertical interconnect access [VIA] connections
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/46—Manufacturing multilayer circuits
- H05K3/4644—Manufacturing multilayer circuits by building the multilayer layer by layer, i.e. build-up multilayer circuits
Landscapes
- Production Of Multi-Layered Print Wiring Board (AREA)
- Manufacturing Of Printed Wiring (AREA)
Description
【０００１】[0001]
【産業上の利用分野】本発明は、多層印刷配線板の製造
方法に関し、特に層間絶縁層に上下配線層を接続するバ
イアホールを形成する多層印刷配線板の製造方法に関す
るものである。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a multilayer printed wiring board, and more particularly to a method for manufacturing a multilayer printed wiring board in which via holes for connecting upper and lower wiring layers are formed in an interlayer insulating layer.
【０００２】[0002]
【従来の技術】電子装置の電子部品実装の高密度化に伴
い、電子装置に使用される印刷配線板も高密度化が要求
され、層間絶縁層に上下配線を接続するバイアホールを
有する多層印刷配線板が使用されている。従来、絶縁層
にバイアホールを形成する多層印刷配線板の製造方法と
して、次のような方法が知られており、図３、図４、及
び図５に示す。2. Description of the Related Art As electronic components are mounted in electronic devices at higher densities, printed wiring boards used in electronic devices are also required to have higher densities. Multilayer printing having via holes for connecting upper and lower wiring to an interlayer insulating layer is required. Wiring boards are used. Conventionally, the following method is known as a method for manufacturing a multilayer printed wiring board in which a via hole is formed in an insulating layer, and is shown in FIGS. 3, 4, and 5.
【０００３】従来例として、絶縁層の上にめっきにより
付加的に導電回路を形成し、バイアホールを形成する多
層印刷配線板の製造技術を図３（ａ）〜（ｄ）、図４
（ｅ）（ｆ）を用いて説明する。図３（ａ）は回路形
成、（ｂ）は黒化処理、（ｃ）は絶縁層形成、（ｄ）は
現像、図４（ｅ）は研磨、粗化、（ｆ）はめっきであ
る。As a conventional example, a manufacturing technique of a multilayer printed wiring board in which a conductive circuit is additionally formed by plating on an insulating layer to form a via hole is shown in FIGS. 3 (a) to 3 (d) and FIG.
This will be described with reference to (e) and (f). 3A shows circuit formation, FIG. 3B shows blackening treatment, FIG. 3C shows insulating layer formation, FIG. 3D shows development, FIG. 4E shows polishing and roughening, and FIG. 4F shows plating.
【０００４】まず、図３（ａ）に示すように、エポキシ
ガラス材料等の基板（１）上に塩化第二鉄水溶液等で銅
箔をエッチングし、導電回路（２）を形成する。次いで
酸性塩化第二銅水溶液で導電回路（２）表面を粗面化
後、アルカリ性過硫酸カリウム水溶液等で導電回路表面
を酸化し酸化銅（３）を形成する（図３（ｂ），
（ｂ′））。この酸化銅形成は導電回路と絶縁層の密着
を向上させるために印刷配線板に広く使用されている技
術である。First, as shown in FIG. 3A, a copper foil is etched on a substrate (1) made of an epoxy glass material or the like with a ferric chloride aqueous solution or the like to form a conductive circuit (2). Next, after the surface of the conductive circuit (2) is roughened with an aqueous cupric acid chloride solution, the surface of the conductive circuit is oxidized with an aqueous solution of alkaline potassium persulfate to form copper oxide (3) (FIG. 3 (b),
(B ')). This copper oxide formation is a technique widely used for printed wiring boards to improve the adhesion between the conductive circuit and the insulating layer.
【０００５】次に、図３（ｃ）に示すように、基板
（１）上に感光性液状絶縁樹脂等を数十μｍ厚さに塗
布、乾燥し、絶縁層（４）を形成する。次いで紫外線を
照射し、バイアホール形成以外の絶縁層（４）表面を硬
化後現像し、バイアホール（８）を形成する（図３
（ｄ））。熱硬化後、過マンガン酸塩水溶液で絶縁層
（４）表面を化学的に粗化し後、硫酸水溶液等で中和処
理する。絶縁層表面には、図４（ｅ）のように、粗化面
（６）が形成される。次いで無電解銅めっきと電気銅め
っきで導電層（７）を形成する（図４（ｆ））。このよ
うな工程を繰り返し多層印刷配線板が製造される。Next, as shown in FIG. 3C, a photosensitive liquid insulating resin or the like is applied on the substrate (1) to a thickness of several tens μm and dried to form an insulating layer (4). Next, the surface of the insulating layer (4) other than the formation of the via hole is cured and developed by irradiating ultraviolet rays to form a via hole (8) (FIG. 3).
(D)). After thermosetting, the surface of the insulating layer (4) is chemically roughened with a permanganate aqueous solution, and then neutralized with a sulfuric acid aqueous solution or the like. A roughened surface (6) is formed on the surface of the insulating layer as shown in FIG. Next, a conductive layer (7) is formed by electroless copper plating and electrolytic copper plating (FIG. 4 (f)). These steps are repeated to produce a multilayer printed wiring board.
【０００６】もう一の従来例として、バイアホールの形
成に、レーザー加工を応用した第二の印刷配線板の製造
技術が特開昭６１−９５７９２で開示されている。この
従来例を図５（ａ）〜（ｄ）を用いて説明する。図５
（ａ）は回路形成、（ｂ）はレーザー加工、（ｃ）は粗
化、（ｄ）はめっきである。図５（ａ）に示すように、
エポキシガラス材料等の基板（１）上に塩化第二鉄水溶
液等で銅箔（１１）をエッチングし、金属箔除去部分を
形成する。次いで金属箔除去部分にレーザー光を照射す
ることによりバイアホール（８）を形成する（図５
（ｂ））。次に、図５（ｃ）（ｄ）に示すように、粗化
を行い、めっきを行う。このような工程を繰り返し多層
印刷配線板が製造される。As another conventional example, Japanese Patent Application Laid-Open No. 61-95792 discloses a technique for manufacturing a second printed wiring board using laser processing for forming a via hole. This conventional example will be described with reference to FIGS. FIG.
(A) shows circuit formation, (b) shows laser processing, (c) shows roughening, and (d) shows plating. As shown in FIG.
A copper foil (11) is etched on a substrate (1) made of an epoxy glass material or the like with an aqueous ferric chloride solution or the like to form a metal foil removed portion. Then, a laser beam is applied to the metal foil removed portion to form a via hole (8) (FIG. 5).
(B)). Next, as shown in FIGS. 5C and 5D, roughening is performed and plating is performed. These steps are repeated to produce a multilayer printed wiring board.
【０００７】[0007]
【発明が解決しようとする課題】上記従来例の第１の技
術では、バイアホール壁と絶縁樹脂表面をめっきの密着
性を向上するため過マンガン酸塩水溶液で処理する時
に、導電回路表面の酸化銅が侵され、バイアホール底部
のベース回路と絶縁樹脂の境界から過マンガン酸塩水溶
液がしみこみベース回路と絶縁樹脂の剥離現象（ハロー
イング現象（１２））が生じ、部品実装等のはんだ付け
熱による印刷配線板の膨れの発生が生じるといった問題
点がある。In the first technique of the prior art, when the via hole wall and the insulating resin surface are treated with an aqueous solution of permanganate to improve the adhesion of plating, the surface of the conductive circuit is oxidized. The copper is attacked, the permanganate solution penetrates from the boundary between the base circuit and the insulating resin at the bottom of the via hole, and the base circuit and the insulating resin peel off (haloing phenomenon (12)). There is a problem that swelling of the printed wiring board occurs due to the above.
【０００８】また、上記従来例の第２の技術では、絶縁
層の厚みが厚い場合の加工時間の増加やレーザー光でバ
イアホール形成後は過マンガン酸塩水溶液等での処理が
必要であるので上記従来例第１の技術と同様の問題点が
ある。本発明では、バイアホール底部に絶縁層を薄くし
た状態で残し、過マンガン酸塩水溶液等で基板を処理す
るときのベース回路表面のハローイングを防ぎ、かつレ
ーザー加工時間の短縮を実現する。In the second technique of the prior art, the processing time is increased when the thickness of the insulating layer is large, and the treatment with a permanganate aqueous solution or the like is required after forming the via hole with laser light. There is a problem similar to that of the first prior art. In the present invention, the insulating layer is left thin at the bottom of the via hole to prevent haloing of the base circuit surface when the substrate is treated with a permanganate aqueous solution or the like, and to shorten the laser processing time.
【０００９】[0009]
【課題を解決するための手段】本発明は、基板上に形成
された導電回路表面に酸化銅を形成後、第一の絶縁層を
形成する工程と、前記第一の絶縁層上に第二の絶縁層を
形成する工程と、前記第二の絶縁層表面を研磨、粗化す
る工程と前記第二の絶縁層表面に導電層を形成する工程
と前記導電層を回路形成してバイアホール形成時のマス
クを形成する工程（バイアホール部の導電層の除去）
と、前記第二の絶縁層にバイアホールを形成する工程
と、バイアホール壁面を粗化する工程と、バイアホール
底部の前記第一の絶縁層を除去する工程と、めっきによ
り前記バイアホール部に導電層を形成する工程を含む多
層印刷配線板の製造方法である。SUMMARY OF THE INVENTION The present invention comprises a step of forming a first insulating layer after forming copper oxide on the surface of a conductive circuit formed on a substrate, and a step of forming a second insulating layer on the first insulating layer. Forming an insulating layer, polishing and roughening the surface of the second insulating layer, forming a conductive layer on the surface of the second insulating layer, and forming a via hole by forming a circuit on the conductive layer. Of forming a mask when removing (removal of conductive layer in via hole)
Forming a via hole in the second insulating layer, roughening the via hole wall surface, removing the first insulating layer at the bottom of the via hole, and plating the via hole portion. It is a method for manufacturing a multilayer printed wiring board including a step of forming a conductive layer.
【００１０】また、本発明は、基板上に形成された導電
回路表面に酸化銅を形成後、第一の絶縁層を形成する工
程と、前記第一の絶縁層上に第二の絶縁層を形成する工
程と、前記第二の絶縁層表面をアルカリ性過マンガン酸
塩水溶液で粗化処理する工程と、前記第二の絶縁層表面
に無電解めっきにより導電層を形成する工程と、前記導
電層を回路形成してバイアホール形成時のマスクを形成
する工程（バイアホール部の導電層の除去）と、前記第
二の絶縁層にバイアホールを形成する工程とバイアホー
ル壁面をアルカリ性過マンガン酸塩水溶液で粗化処理す
る工程とバイアホール底部の前記第一の絶縁層をレーザ
ー光により除去する工程と、めっきにより前記バイアホ
ールに導電層を形成する工程を含むことを特徴とする多
層印刷配線板の製造方法である。The present invention also provides a step of forming a first insulating layer after forming copper oxide on the surface of a conductive circuit formed on a substrate, and forming a second insulating layer on the first insulating layer. Forming, roughening the surface of the second insulating layer with an aqueous solution of alkaline permanganate, forming a conductive layer on the surface of the second insulating layer by electroless plating, Forming a mask when forming a via hole by removing a circuit (removal of a conductive layer in a via hole portion); forming a via hole in the second insulating layer; A multi-layer printed wiring board comprising a step of performing a roughening treatment with an aqueous solution, a step of removing the first insulating layer at the bottom of the via hole by a laser beam, and a step of forming a conductive layer in the via hole by plating. Made of It is a method.
【００１１】[0011]
【作用】本発明においては、基板上の回路を酸化銅に
し、基板上に感光性液状樹脂を塗布し、第１の絶縁層を
形成し、その上に第２絶縁層を塗り、粗化、めっきを行
い、第２の絶縁層のバイアホール部を現像し、後工程の
粗化処理のマスクを形成するもので、バイアホール底部
に第一の絶縁層を薄く残し、粗化を行い、その後レーザ
ーにより上記バイアホール部の絶縁層を除去するためバ
イアホール底部にある導電回路のハローイング現象が防
止できるものであり、また、バイアホール底部に絶縁層
を薄くした状態で残し、過マンガン酸塩水溶液等で基板
を処理するときのベース回路表面のハローイングを防
ぎ、かつレーザー加工時間の短縮を実現することができ
るものである。According to the present invention, a circuit on a substrate is made of copper oxide, a photosensitive liquid resin is applied on the substrate, a first insulating layer is formed, and a second insulating layer is coated thereon, Plating is performed, and the via-hole portion of the second insulating layer is developed to form a mask for a roughening process in a later step. The first insulating layer is left thin at the bottom of the via-hole, and roughening is performed. The insulating layer at the via hole is removed by a laser, so that the haloing phenomenon of the conductive circuit at the bottom of the via hole can be prevented.Also, the insulating layer is left thin at the bottom of the via hole, and the permanganate is removed. It is possible to prevent haloing of the surface of the base circuit when treating the substrate with an aqueous solution or the like, and to shorten the laser processing time.
【００１２】[0012]
【実施例】本発明の実施例について図面を参照して説明
する。図１、図２は本発明の実施例の断面図で、図１
（ａ）は回路形成、（ｂ）は黒化処理、（ｃ）は第１絶
縁層形成、（ｄ）は第２絶縁層形成、研磨、粗化、
（ｅ）はめっき、（ｆ）は回路形成（レーザー加工時の
マスク形成）および図２（ｇ）は現像、粗化、（ｈ）は
レーザー加工、（ｉ）はめっきである。図１、図２に示
すように、基板上に形成された導電回路（２）表面に酸
化銅（３）を形成後、第一の絶縁層（４）を基板上に形
成する工程と前記第一の絶縁層（４）上に第二の絶縁層
（５）を形成する工程と前記第二の絶縁層（５）表面を
アルカリ性過マンガン酸塩水溶液で処理する工程と前記
第二の絶縁層（５）表面に無電解めっきにより導電層
（７）を形成する工程と前記第二の絶縁層（５）にバイ
アホール（８）を形成する工程とバイアホール底部
（９）の前記第一の絶縁層をレーザー光により除去する
工程とめっきにより前記バイアホール（８）に導電層
（１０）を形成する工程を含むことを特徴とする多層印
刷配線板の製造方法である。Embodiments of the present invention will be described with reference to the drawings. 1 and 2 are sectional views of an embodiment of the present invention.
(A) circuit formation, (b) blackening treatment, (c) first insulating layer formation, (d) second insulating layer formation, polishing, roughening,
(E) is plating, (f) is circuit formation (mask formation during laser processing) and FIG. 2 (g) is development and roughening, (h) is laser processing, and (i) is plating. As shown in FIGS. 1 and 2, after forming copper oxide (3) on the surface of a conductive circuit (2) formed on a substrate, forming a first insulating layer (4) on the substrate, A step of forming a second insulating layer (5) on one insulating layer (4), a step of treating the surface of the second insulating layer (5) with an aqueous solution of alkaline permanganate, and a step of forming the second insulating layer (5) a step of forming a conductive layer (7) on the surface by electroless plating, a step of forming a via hole (8) in the second insulating layer (5), and the first step of forming a via hole bottom (9). A method for manufacturing a multilayer printed wiring board, comprising a step of removing an insulating layer by a laser beam and a step of forming a conductive layer (10) in the via hole (8) by plating.
【００１３】より詳しく説明すると、まず、図１（ａ）
に示すように、エポキシガラス材料等の基板（１）上に
塩化第二鉄水溶液等で銅箔（例えば１８μｍ厚銅箔をエ
ッチングし、導電回路（２）を形成する。次いで、図１
（ｂ）に示すように、酸性塩化第二銅水溶液で導電回路
（２）表面を粗面化後、アルカリ性過硫酸カリウム水溶
液、アルカリ性亜塩素酸ナトリウム水溶液、硫化カリー
塩化アンモニア水溶液等で導電回路表面を酸化し酸化銅
（３）を形成する。More specifically, first, FIG.
As shown in FIG. 1, a conductive circuit (2) is formed on a substrate (1) made of an epoxy glass material or the like by etching a copper foil (for example, an 18 μm thick copper foil) with an aqueous ferric chloride solution or the like.
As shown in (b), after the surface of the conductive circuit (2) is roughened with an aqueous solution of acidic cupric chloride, the surface of the conductive circuit is exposed with an aqueous solution of alkaline potassium persulfate, an aqueous solution of alkaline sodium chlorite, or an aqueous solution of curly sulfide ammonium chloride. Is oxidized to form copper oxide (3).
【００１４】次に、図１（ｃ）に示すように、感光性液
状絶縁樹脂（例えばエポキシ樹脂）をカーテンコータ
ー、ロールコーター、スクリーン印刷等の方法で上記基
板（１）上に塗布する。例えば、カーテンコーターで１
０μｍ厚に塗布し、指触乾燥（９０℃、１時間）、熱硬
化（１４０℃、１時間）して第一絶縁層（４）（完全硬
化層）を形成する。次いで、図１（ｄ）に示すように、
第一絶縁層（４）上に、更に液状絶縁樹脂（例えばエポ
キシ樹脂）を７０μｍ厚に塗布して指触乾燥（９０℃、
１時間）を行う。これは、第二絶縁層（５）（半硬化
層）の形成である。Next, as shown in FIG. 1C, a photosensitive liquid insulating resin (for example, epoxy resin) is applied onto the substrate (1) by a method such as a curtain coater, a roll coater, and screen printing. For example, one with a curtain coater
It is applied to a thickness of 0 μm, dried by touch (90 ° C., 1 hour), and thermally cured (140 ° C., 1 hour) to form a first insulating layer (4) (fully cured layer). Then, as shown in FIG.
A liquid insulating resin (for example, epoxy resin) is further applied to a thickness of 70 μm on the first insulating layer (4), and is dried by touch (90 ° C.,
1 hour). This is the formation of the second insulating layer (5) (semi-cured layer).
【００１５】そして、ベルトサンダー、ジェットスクラ
ブ、バフ等により第二絶縁層（５）の表面を約２０μｍ
研磨する。アルカリ性水溶液（アルカリ規定度：０．７
〜０．８Ｎ，７０〜８０℃）で膨潤をし、アルカリ性過
マンガン酸塩水溶液（ＫＭｎＯ４：４０〜６０ｇ／ｌ、
アルカリ規定度：１．０〜１．２Ｎ，６０〜８０℃）で
化学的に粗化し、硫酸（０．３〜０．４Ｎ，４０〜５０
℃）で中和することにより、第二絶縁層（５）表面に粗
化面（６）が形成される。Then, the surface of the second insulating layer (5) is about 20 μm by a belt sander, a jet scrub, a buff or the like.
Grind. Alkaline aqueous solution (alkaline normality: 0.7
～0.8N, and swelling at 70 to 80 ° C.), an alkaline permanganate aqueous solution (KMnO 4: 40~60g / l,
It is chemically roughened at an alkali normality of 1.0 to 1.2 N, 60 to 80 ° C., and sulfuric acid (0.3 to 0.4 N, 40 to 50 N).
C), a roughened surface (6) is formed on the surface of the second insulating layer (5).
【００１６】次に、図１（ｅ）に示すように、、無電解
銅めっき液中（エチレンジアミン四酢酸塩：３０ｇ／
ｌ、銅イオン：２〜３ｇ／ｌ，ＮａＯＨ：９〜１２ｇ／
ｌ，ＨＣＨＯ：３〜６ｇ／ｌ，ｐＨ：１２〜１４）に約
２０分浸漬し、約０．３〜０．６μｍ銅めっき層を形成
し、次いで電気銅めっきを行い約１０μｍの導電層
（７）を形成する。次いで、バイアホール形成部の銅め
っき層を塩化第二鉄水溶液等でエッチングし、図１
（ｆ）のように回路形成して、第二絶縁層（５）の現像
時のマスクを形成する。Next, as shown in FIG. 1E, in an electroless copper plating solution (ethylenediaminetetraacetate: 30 g /
1, copper ion: 2-3 g / l, NaOH: 9-12 g /
1, HCHO: 3 to 6 g / l, pH: 12 to 14) for about 20 minutes to form a copper plating layer of about 0.3 to 0.6 μm, followed by electrolytic copper plating to form a conductive layer of about 10 μm ( 7) is formed. Next, the copper plating layer in the via hole forming portion was etched with a ferric chloride aqueous solution or the like, and FIG.
A circuit is formed as shown in (f), and a mask for developing the second insulating layer (5) is formed.
【００１７】次いで、γブチルラクタンを含む現像液で
現像を行い、直径１５０μｍのバイアホール（８）を形
成する（図２（ｇ））。次いで、上述した第二絶縁層
（５）表面の粗化面（図１（ｄ））と同様に、化学的に
粗化を行う。次いで、図２（ｈ）に示すように、エキシ
マレーザー、ＹＡＧレーザー、ＣＯ２レーザー等により
レーザー光線を照射し、バイアホール底部（９）の第一
の絶縁層（４）（エポキシ樹脂層）を除去し、導電回路
（２）表面を露出させる。Next, development is performed with a developer containing γ-butyl lactan to form a via hole (8) having a diameter of 150 μm (FIG. 2 (g)). Next, chemical roughening is performed in the same manner as the above-described roughened surface of the second insulating layer (5) (FIG. 1D). Next, as shown in FIG. 2H, a laser beam is irradiated by an excimer laser, a YAG laser, a CO 2 laser or the like to remove the first insulating layer (4) (epoxy resin layer) at the bottom of the via hole (9). Then, the surface of the conductive circuit (2) is exposed.
【００１８】ここでは、エキシマレーザーにて１Ｊ／ｃ
ｍ２の強度の紫外光（２００〜３００ｎｍ）を照射し
た。レーザーにより除去する絶縁層の膜厚は、１０μｍ
と薄いので６０μｍ厚の時と比較すると加工時間は１／
６と短縮される。次いで、熱硬化（１４０℃、１時間）
を行う。Here, an excimer laser is used to obtain 1 J / c.
Irradiation with ultraviolet light (200 to 300 nm) having an intensity of m 2 was performed. The thickness of the insulating layer to be removed by laser is 10 μm
Processing time is 1 /
It is shortened to 6. Next, heat curing (140 ° C, 1 hour)
I do.
【００１９】次いで、図１（ｉ）に示すように、無電解
銅めっき、電気銅めっきを行い２０μｍの導電層（１
０）を形成する。また、無電解銅めっきのみで導通層を
形成しても良い。上述したような工程を繰り返して多層
印刷配線板が製造される。上記実施例に基づいて製造さ
れた多層印刷配線板のバイアホール底部の導電回路と第
一の絶縁樹脂との界面にはハローイングは生じなかっ
た。Then, as shown in FIG. 1 (i), electroless copper plating and electrolytic copper plating were performed to form a 20 μm conductive layer (1).
0) is formed. Further, the conductive layer may be formed only by electroless copper plating. By repeating the steps described above, a multilayer printed wiring board is manufactured. No haloing occurred at the interface between the conductive circuit at the bottom of the via hole and the first insulating resin of the multilayer printed wiring board manufactured according to the above-described embodiment.
【００２０】[0020]
【発明の効果】以上説明したように、本発明によれば、
バイアホール底部に第一の絶縁層を薄く残し、粗化を行
い、その後レーザーにより上記バイアホール部の絶縁層
を除去するためバイアホール底部にある導電回路のハロ
ーイング現象が防止できる効果を有する。また、バイア
ホール形成時レーザー照射の加工時間短縮が図れるとい
う効果を奏するものである。As described above, according to the present invention,
Since the first insulating layer is left thin at the bottom of the via hole, roughening is performed, and then the insulating layer at the via hole is removed by laser. This has the effect of preventing the halo phenomenon of the conductive circuit at the bottom of the via hole. Also, there is an effect that the processing time of laser irradiation during via hole formation can be shortened.
【図１】 本発明の実施例の工程を示す断面図。FIG. 1 is a cross-sectional view illustrating a process of an embodiment of the present invention.
【図２】 本発明の実施例の図１に続く工程を示す断面
図。FIG. 2 is a sectional view showing a step following FIG. 1 in the embodiment of the present invention;
【図３】 従来技術を示す断面図。FIG. 3 is a sectional view showing a conventional technique.
【図４】 従来技術を示す断面図。FIG. 4 is a sectional view showing a conventional technique.
【図５】 もう一の従来技術を示す断面図。FIG. 5 is a sectional view showing another conventional technique.
１ 基板 ２ 導電回路 ３ 酸化銅 ４ 第１絶縁層 ５ 第２絶縁層 ６ 粗化面 ７ 導電層 ８ バイアホール ９ バイアホール底部 １０ 導電層 １１ 銅箔 １２ ハローイング現象 DESCRIPTION OF SYMBOLS 1 Substrate 2 Conductive circuit 3 Copper oxide 4 First insulating layer 5 Second insulating layer 6 Roughened surface 7 Conductive layer 8 Via hole 9 Via hole bottom 10 Conductive layer 11 Copper foil 12 Hello phenomenon
Claims (2)
銅を形成後、第一の絶縁層を形成する工程と、前記第一
の絶縁層上に第二の絶縁層を形成する工程と、前記第二
の絶縁層表面を研磨、粗化する工程と前記第二の絶縁層
表面に導電層を形成する工程と前記導電層を回路形成し
てバイアホール形成時のマスクを形成する工程と、前記
第二の絶縁層にバイアホールを形成する工程と、バイア
ホール壁面を粗化する工程と、バイアホール底部の前記
第一の絶縁層を除去する工程と、めっきにより前記バイ
アホール部に導電層を形成する工程を含む多層印刷配線
板の製造方法。A step of forming a first insulating layer after forming copper oxide on a surface of a conductive circuit formed on a substrate; and a step of forming a second insulating layer on the first insulating layer. A step of polishing and roughening the surface of the second insulating layer, a step of forming a conductive layer on the surface of the second insulating layer, and a step of forming a mask when forming a via hole by forming a circuit on the conductive layer. Forming a via hole in the second insulating layer, roughening the wall surface of the via hole, removing the first insulating layer at the bottom of the via hole, and electrically connecting the via hole by plating. A method for manufacturing a multilayer printed wiring board including a step of forming a layer.
銅を形成後、第一の絶縁層を形成する工程と、前記第一
の絶縁層上に第二の絶縁層を形成する工程と、前記第二
の絶縁層表面をアルカリ性過マンガン酸塩水溶液で粗化
処理する工程と、前記第二の絶縁層表面に無電解めっき
により導電層を形成する工程と、前記導電層を回路形成
してバイアホール形成時のマスクを形成する工程と、前
記第二の絶縁層にバイアホールを形成する工程とバイア
ホール壁面をアルカリ性過マンガン酸塩水溶液で粗化処
理する工程とバイアホール底部の前記第一の絶縁層をレ
ーザー光により除去する工程と、めっきにより前記バイ
アホールに導電層を形成する工程を含むことを特徴とす
る多層印刷配線板の製造方法。2. A step of forming a first insulating layer after forming copper oxide on a surface of a conductive circuit formed on a substrate; and a step of forming a second insulating layer on the first insulating layer. A step of roughening the surface of the second insulating layer with an aqueous solution of alkaline permanganate, a step of forming a conductive layer on the surface of the second insulating layer by electroless plating, and forming a circuit on the conductive layer. Forming a mask at the time of forming a via hole, forming a via hole in the second insulating layer, roughening the wall surface of the via hole with an aqueous solution of alkaline permanganate, and forming the via hole at the bottom of the via hole. A method for manufacturing a multilayer printed wiring board, comprising: a step of removing one insulating layer by a laser beam; and a step of forming a conductive layer in the via hole by plating.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP9016295A JP2699920B2 (en) | 1995-03-23 | 1995-03-23 | Method for manufacturing multilayer printed wiring board |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP9016295A JP2699920B2 (en) | 1995-03-23 | 1995-03-23 | Method for manufacturing multilayer printed wiring board |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH08264957A JPH08264957A (en) | 1996-10-11 |
| JP2699920B2 true JP2699920B2 (en) | 1998-01-19 |
Family
ID=13990799
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP9016295A Expired - Fee Related JP2699920B2 (en) | 1995-03-23 | 1995-03-23 | Method for manufacturing multilayer printed wiring board |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP2699920B2 (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5919799A (en) * | 1995-03-13 | 1999-07-06 | Nikken Chemicals Co., Ltd. | Imidazothiazole compound |
Families Citing this family (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP3398557B2 (en) * | 1997-01-29 | 2003-04-21 | インターナショナル・ビジネス・マシーンズ・コーポレーション | Method of manufacturing surface wiring printed circuit board |
| JP3399434B2 (en) | 2001-03-02 | 2003-04-21 | オムロン株式会社 | Method for forming plating of polymer molding material, circuit forming part, and method for manufacturing this circuit forming part |
| DE10348715B4 (en) | 2003-10-16 | 2006-05-04 | Infineon Technologies Ag | Method for producing a leadframe with improved adhesion between it and plastic as well as leadframe |
| KR101022914B1 (en) * | 2008-11-04 | 2011-03-16 | 삼성전기주식회사 | Method of manufacturing printed circuit board |
| JP2012186385A (en) * | 2011-03-07 | 2012-09-27 | Fujitsu Component Ltd | Production method of wiring board coated with underfill, and wiring board produced by this production method |
-
1995
- 1995-03-23 JP JP9016295A patent/JP2699920B2/en not_active Expired - Fee Related
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5919799A (en) * | 1995-03-13 | 1999-07-06 | Nikken Chemicals Co., Ltd. | Imidazothiazole compound |
Also Published As
| Publication number | Publication date |
|---|---|
| JPH08264957A (en) | 1996-10-11 |
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