JPH1140951A - Manufacture of multilayred wiring board - Google Patents
Manufacture of multilayred wiring boardInfo
- Publication number
- JPH1140951A JPH1140951A JP18945697A JP18945697A JPH1140951A JP H1140951 A JPH1140951 A JP H1140951A JP 18945697 A JP18945697 A JP 18945697A JP 18945697 A JP18945697 A JP 18945697A JP H1140951 A JPH1140951 A JP H1140951A
- Authority
- JP
- Japan
- Prior art keywords
- wiring board
- multilayer wiring
- insulating resin
- conductive
- manufacturing
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Abstract
Description
【０００１】[0001]
【発明の属する技術分野】本発明は、配線基板の製造方
法に関わり、特に、感光性層間絶縁樹脂膜を有する高密
度な多層配線基板の製造方法に関する。The present invention relates to a method of manufacturing a wiring board, and more particularly to a method of manufacturing a high-density multilayer wiring board having a photosensitive interlayer insulating resin film.
【０００２】[0002]
【従来の技術】電子機器の高機能化及び半導体デバイス
の高集積化に伴い、配線基板も高密度化が求められてお
り、現在では多層基板がその主流となっている。多層配
線基板の製造法としては、大きく分けて積層接着法とビ
ルドアップ法の２種類が広く知られている。積層接着法
は、内層となる積層板にドリルによりブラインドバイヤ
ホールを形成するブラインド孔を開けて、これにめっき
を施すことによりブラインドバイヤホールを有する積層
板を形成し、このブラインドバイヤホールを有する積層
板に外層を積層プレスした後、スルーホール孔を開け、
めっきすることにより多層配線板を製造する方法であ
る。2. Description of the Related Art As electronic devices have become more sophisticated and semiconductor devices have become more highly integrated, there has been a demand for higher density of wiring substrates, and multilayer substrates are now the mainstream. As a method of manufacturing a multilayer wiring board, there are broadly known two types, a lamination bonding method and a build-up method. The laminating method uses a drill to form a blind via hole in a laminated plate serving as an inner layer, and forms a laminated plate having a blind via hole by plating the blind hole. After laminating and pressing the outer layer on the board, drill through holes,
This is a method of manufacturing a multilayer wiring board by plating.
【０００３】しかしながら、上記積層接着法において
は、層間接続を行うためのブラインドバイヤホールやス
ルーホールがメカニカルなドリリングによって開けられ
るためにその寸法が比較的大きく、配線密度を上げるの
が難しい。特に近年、民生用各種電子機器等の小型化や
薄型化に伴い、所定の電気回路を構成する配線基板を収
納するスペースは非常に限られたものとなってきてお
り、この限られたスペース内に所望通りの電気回路を構
成する配線基板を収納するためには、感光性樹脂を用い
た微細なフォトビアホールにより各層間の導通をとるビ
ルドアップ法による薄板化と高密度化が有力な技術とな
ってきている。However, in the above-mentioned laminating method, since blind via holes and through holes for making interlayer connections are opened by mechanical drilling, their dimensions are relatively large, and it is difficult to increase the wiring density. In recent years, in recent years, as various types of consumer electronic devices have become smaller and thinner, the space for accommodating wiring boards constituting a predetermined electric circuit has become very limited. In order to accommodate the wiring board that composes the desired electric circuit, thinning and high density by the build-up method that takes conduction between each layer by fine photo via holes using photosensitive resin is an effective technology. It has become to.
【０００４】層間絶縁膜に感光性樹脂を用いたビルドア
ップ法による多層配線基板の製造方法については、例え
ば特開平４−１４８５９０号公報がある。この配線基板
は、基材にガラスエポキシ銅張積層板を使用し、絶縁膜
は感光性エポキシ樹脂、導体層は銅めっきをもって順次
積層した構造からなっている。ビルドアップ法による多
層配線基板の製造方法においては、絶縁層と導体回路、
特に絶縁層上の導体回路が強固に接着していることが非
常に重要となる。A method of manufacturing a multilayer wiring board by a build-up method using a photosensitive resin for an interlayer insulating film is disclosed in, for example, Japanese Patent Application Laid-Open No. 4-148590. This wiring board has a structure in which a glass epoxy copper-clad laminate is used as a base material, an insulating film is photosensitive epoxy resin, and a conductor layer is sequentially laminated by copper plating. In a method of manufacturing a multilayer wiring board by a build-up method, an insulating layer and a conductive circuit,
In particular, it is very important that the conductor circuit on the insulating layer is firmly bonded.
【０００５】この絶縁層上に導体回路を強固に接着する
技術としては、例えば特開平６−２６０７６３号公報あ
るいは特開平７−１５１３９号公報に示されるように、
クロム酸または過マンガン酸カリウム溶液で絶縁層を粗
化し、その表面に導体層を形成する方法が広く行われて
いる。この際、粗化後の樹脂に凹凸形状を形成して導体
回路とのアンカー効果を強く持たせるために、感光性樹
脂中に無機充填剤を用いることが多い。As a technique for firmly bonding a conductor circuit on the insulating layer, for example, as disclosed in JP-A-6-260763 or JP-A-7-15139,
2. Description of the Related Art A method of roughening an insulating layer with a chromic acid or potassium permanganate solution and forming a conductor layer on the surface thereof has been widely used. At this time, an inorganic filler is often used in the photosensitive resin in order to form an uneven shape on the roughened resin and to have a strong anchor effect with the conductor circuit.
【０００６】[0006]
【発明が解決しようとする課題】粗化工程は、ビルドア
ップ法において不可欠、最重要な工程であるが、同時に
粗化工程に付随して下記のような問題が生じるために、
ビルドアップ基板の高密度、高精細化の障害ともなって
いる。The roughening step is indispensable and the most important step in the build-up method. At the same time, however, the following problems occur accompanying the roughening step.
This is an obstacle to high density and high definition of the build-up substrate.
【０００７】第一は、導体回路の線間絶縁性の問題であ
る。なすわち、ビルドアップ法では、樹脂上の導体回路
との接着を高めるために、粗化によって樹脂中の無機充
填剤あるいは逆に樹脂を溶解させることにより、絶縁樹
脂表面上に多孔の凹凸形状を形成している。この後、全
面めっきを施してエッチングにより導体回路を形成する
が、導体回路形成後の回路間樹脂表面には、粗化工程時
に形成された多孔の凹凸がそのままの形状で存在してい
る。この間隙の多い絶縁樹脂層は、恒温恒湿試験中に水
蒸気が浸透、吸湿しやすいために導体回路近傍で金属の
溶解すなわちマイグレーションが促進されやすい。The first problem is the problem of line insulation of the conductor circuit. In other words, in the build-up method, in order to enhance the adhesion with the conductor circuit on the resin, the inorganic filler in the resin is dissolved by roughening or, conversely, the resin is dissolved to form a porous uneven surface on the insulating resin surface. Is formed. Thereafter, the entire surface is plated to form a conductive circuit by etching. However, on the resin surface between the circuits after the formation of the conductive circuit, the porous irregularities formed during the roughening step are present in the same shape. In the insulating resin layer having many gaps, water vapor easily penetrates and absorbs moisture during the constant temperature and constant humidity test, so that the dissolution or migration of the metal in the vicinity of the conductor circuit is easily promoted.
【０００８】特に最外層のソルダレジストに覆われてい
ない導体回路間では、直接外気に晒される結果、結露し
やすくマイグレーションの進行も内層に比較して格段に
早い。また、絶縁樹脂上にめっきで形成した金属層をエ
ッチングして導体回路を形成するときに、樹脂の凹部に
金属が残りやすいこと、さらには、樹脂の凹部に染み込
んだプロセス処理液の洗浄が十分に行われずイオン性残
渣が残りやすいことなどもマイグレーション進行促進に
繋がる。[0008] In particular, conductor circuits that are not covered by the outermost layer of solder resist are directly exposed to the outside air. As a result, dew condensation easily occurs and migration proceeds much faster than that of the inner layer. In addition, when a conductive circuit is formed by etching a metal layer formed by plating on an insulating resin, the metal is likely to remain in the concave portion of the resin, and further, the cleaning of the processing solution penetrated into the concave portion of the resin is sufficient. The fact that ionic residues are likely to remain without being performed also leads to the promotion of migration progress.
【０００９】第二は、導体回路間へのめっき異常析出の
問題である。すなわち、基板の表面パッド上には、半田
を介して部品が搭載されるが、銅パッドそのものだと半
田の食われ量が大きい。そこでリペア耐性を持たせるた
めに通常ニッケルめっきが施され、さらにニッケル膜上
に半田濡れ性を確保するために金めっきが施される。こ
のニッケルめっきあるいは金めっきは、表面パッドの全
てが電気的に接続されているわけではないため、無電界
めっきで行われる。Second, there is a problem of abnormal plating deposition between conductor circuits. That is, components are mounted on the surface pads of the substrate via solder, but the copper pads themselves cause a large amount of solder erosion. Therefore, nickel plating is usually applied to provide repair resistance, and gold plating is applied on the nickel film to ensure solder wettability. This nickel plating or gold plating is performed by electroless plating because not all of the surface pads are electrically connected.
【００１０】しかしながら、導体回路間の樹脂表面に
は、粗化工程時に形成された多孔の凹凸形状を持つ層が
残っており、その凹部には、金属残渣すなわち下地導電
膜形成時の触媒Ｐｄ及び回路形成後の銅エッチング残り
がわずかながら存在する。ニッケルめっきの際には、こ
の金属残渣が核となりニッケルが析出するためにめっき
異常析出が発生する。また、粗化後の樹脂表面には、多
くの孔が存在するため、ニッケルめっきの際に発生した
水素が、導体間の樹脂表面にトラップされやすい。この
水素が活性を持っているとニッケルを還元する結果、ニ
ッケル粒子が析出して導体回路間に付着する。特に導体
回路間の間隔が小さくなるほどこの現象は顕著になる。However, on the resin surface between the conductor circuits, a layer having a porous unevenness formed during the roughening step remains, and in the recess, a metal residue, that is, the catalyst Pd and the catalyst Pd at the time of forming the underlying conductive film are formed. There is a small amount of copper etching residue after circuit formation. At the time of nickel plating, this metal residue becomes a nucleus and nickel is precipitated, so that abnormal plating occurs. In addition, since many holes are present on the roughened resin surface, hydrogen generated during nickel plating is easily trapped on the resin surface between the conductors. If the hydrogen has an activity, it reduces nickel, and as a result, nickel particles precipitate and adhere between the conductor circuits. In particular, this phenomenon becomes more remarkable as the interval between the conductor circuits becomes smaller.
【００１１】上記粗化表面上の金属残渣、イオン性残渣
及び多孔の凹凸形状を持つ樹脂表面層を除去する方法と
しては、例えば研磨等が考えられる。しかしながら、導
体回路間が狭いところでは、導体回路近傍の残渣除去法
が不完全となり、また、研磨法によると導体金属も同時
に削られるため、研磨により削られた導体粉が逆に絶縁
樹脂上に付着する可能性もある。したがって、研磨によ
る物理的除去方法は、対処療法的には利用できても本質
的対策とはなり得ない。As a method of removing the metal residue, the ionic residue, and the resin surface layer having a porous uneven shape on the roughened surface, for example, polishing can be considered. However, where the space between the conductor circuits is narrow, the residue removal method in the vicinity of the conductor circuit becomes incomplete, and according to the polishing method, the conductor metal is also cut at the same time. It may adhere. Therefore, the physical removal method by polishing cannot be an essential countermeasure even if it can be used for coping.
【００１２】本発明の目的は、上記従来の問題点を解決
することにある。すなわち、第一に導体回路間の線間絶
縁性に優れた、信頼性の高い多層配線基板の製造方法を
提供すること、第二に最表面導体回路間隔が狭い場合で
もめっき異常析出がなく、高歩留まりで表面メタライズ
が可能な多層配線基板の製造方法を提供することにあ
る。An object of the present invention is to solve the above conventional problems. That is, firstly, to provide a method for manufacturing a highly reliable multilayer wiring board having excellent line insulation between conductor circuits, and secondly, without plating abnormal deposition even when the outermost conductor circuit interval is narrow, It is an object of the present invention to provide a method of manufacturing a multilayer wiring board capable of surface metallization at a high yield.
【００１３】[0013]
【課題を解決するための手段】上記目的は、導体回路形
成後に、導体回路間の絶縁樹脂表面をエッチングにより
除去することによって達成される。この場合のエッチン
グ方法としては、ドライプロセス及びウエットプロセス
の両方が使用できる。ドライプロセスとしては、Ｏ2プ
ラズマ処理あるいはＵＶ／Ｏ3処理を施した後、水洗工
程を通すことが有効である。上記Ｏ2プラズマ処理とし
ては、純水Ｏ2によるプラズマアッシング及び反応性イ
オンエッチングの他、Ｏ2に種々の割合でＣＦ4を混ぜた
混合ガスによるプラズマアッシング及び反応性イオンエ
ッチングも可能である。The above object is achieved by removing the surface of the insulating resin between the conductor circuits by etching after the formation of the conductor circuits. As an etching method in this case, both a dry process and a wet process can be used. As a dry process, it is effective to pass an O 2 plasma treatment or a UV / O 3 treatment and then pass through a water washing step. As the O 2 plasma treatment, besides plasma ashing and reactive ion etching with pure water O 2 , plasma ashing and reactive ion etching with a mixed gas of O 2 mixed with CF 4 at various ratios are also possible.
【００１４】Ｏ2プラズマ処理あるいはＵＶ／Ｏ3処理を
施すと、反応槽中に生成した化学的に極めて活性な原子
状酸素及び酸素イオンが絶縁樹脂中の有機物と酸化反応
することによって有機物の分解が進む結果、絶縁膜表面
がエッチングされる。この際、絶縁膜表面凹部に存在す
る金属エッチング残渣（下地導電膜形成時の触媒Ｐｄ及
び回路形成後の銅エッチング残り）あるいはイオン性残
渣は、活性種と反応しないために絶縁樹脂表面、特に絶
縁樹脂の分解が進む結果濃縮された無機充填剤上に残
る。When O 2 plasma treatment or UV / O 3 treatment is performed, chemically extremely active atomic oxygen and oxygen ions generated in the reaction tank undergo an oxidation reaction with organic matter in the insulating resin to decompose the organic matter. As a result, the surface of the insulating film is etched. At this time, the metal etching residue (catalyst Pd at the time of forming the underlying conductive film and the copper etching residue after the formation of the circuit) or the ionic residue existing in the concave portion of the insulating film surface does not react with the active species. As the resin decomposes, it remains on the concentrated inorganic filler.
【００１５】しかしながら、Ｏ2プラズマ処理あるいは
ＵＶ／Ｏ3処理により絶縁樹脂表面は親水化されている
ために、次の水洗工程で濃縮された無機充填剤の残渣層
は除去され、さらに残渣層とともに金属残渣やイオン性
残渣も一緒に除去される。すなわち、Ｏ2プラズマ処理
あるいは、ＵＶ／Ｏ3後の導体間絶縁樹脂は、絶縁樹脂
を粗化する前の樹脂表面とほぼ同じ状態になっている。
したがって、恒温恒湿試験中に水蒸気が浸透・吸湿しや
すい多孔の凹凸形状を持つ樹脂表面層及び金属残渣、イ
オン性残渣がないために導体回路近傍での金属溶解すな
わちマイグレーションの促進が抑制される結果、導体回
路間の線間絶縁性が向上する。However, since the surface of the insulating resin is hydrophilized by the O 2 plasma treatment or the UV / O 3 treatment, the residue layer of the inorganic filler concentrated in the next washing step is removed, and further, together with the residue layer Metal and ionic residues are also removed. In other words, the inter-conductor insulating resin after the O 2 plasma treatment or UV / O 3 is almost in the same state as the resin surface before the insulating resin is roughened.
Therefore, since there is no resin surface layer having a porous unevenness and a metal residue and an ionic residue that are easy for water vapor to penetrate and absorb moisture during the constant temperature and humidity test, promotion of metal dissolution, ie, migration, in the vicinity of the conductor circuit is suppressed. As a result, the insulation between lines between the conductor circuits is improved.
【００１６】また、めっき異常析出に関しても導体回路
間の金属残渣がなくなるとともに、ニッケルめっき時に
発生する水素をトラップしやすい多孔の凹凸形状を持つ
樹脂表面層がなく、さらに、プラズマ処理によって樹脂
表面に付加された−ＯＯＨ等によって一部活性水素が酸
化されるために導体回路間へのニッケルの析出が著しく
抑制できる。In addition, with regard to abnormal plating deposition, there is no metal residue between the conductor circuits, and there is no resin surface layer having a porous uneven shape that easily traps hydrogen generated during nickel plating. Since active hydrogen is partially oxidized by the added -OOH or the like, nickel deposition between conductor circuits can be significantly suppressed.
【００１７】プラズマによる酸化処理を利用した回路基
板の製造方法としては、導体回路形成後にプラズマ処理
を施すことにより導体間に残存する触媒Ｐｄを除去し、
めっき時におけるショートの発生を未然に防止する技術
が特開平８−１８６３５１号公報に開示されている。し
かしながら、本発明と本質的に異なる点は、水洗工程の
有無である。As a method of manufacturing a circuit board utilizing an oxidation treatment by plasma, a catalyst Pd remaining between conductors is removed by performing a plasma treatment after a conductor circuit is formed.
A technique for preventing the occurrence of a short circuit during plating is disclosed in Japanese Patent Application Laid-Open No. 8-186351. However, what is essentially different from the present invention is the presence or absence of a water washing step.
【００１８】すなわち、本発明では、上記のごとくＯ2
プラズマ処理等によって絶縁膜表面をエッチングすると
ともに、絶縁膜表面凹部に存在する金属エッチング残渣
（下地導電膜形成時の触媒Ｐｄ及び回路形成後の銅エッ
チング残り）あるいはイオン性残渣を絶縁樹脂の分解の
結果濃縮された無機充填剤上に残存させ、次の水洗工程
で無機充填剤の濃縮残渣層とともに金属残渣やイオン性
残渣を一緒に除去している。上記開示技術のごとく、プ
ラズマ処理のみでは金属及びイオン性残渣の除去効果が
ほとんどなく、かえって無機充填剤の濃縮残渣層が残る
ために、線間絶縁性は低下する結果となる。That is, according to the present invention, as described above, O 2
The surface of the insulating film is etched by plasma treatment or the like, and the metal etching residue (catalyst Pd at the time of forming the underlying conductive film and the copper etching residue after forming the circuit) or the ionic residue existing at the concave portion of the insulating film surface is decomposed by the decomposition of the insulating resin. As a result, the residue is left on the concentrated inorganic filler, and a metal residue and an ionic residue are removed together with the concentrated residue layer of the inorganic filler in the next washing step. As in the above disclosed technique, the plasma treatment alone has almost no effect of removing metal and ionic residues, and instead a concentrated residue layer of the inorganic filler remains. As a result, the line insulation is reduced.
【００１９】一方、ウエットエッチとしては、例えば、
クロム酸、クロム酸塩、重クロム酸塩、マンガン酸塩、
過マンガン酸塩等の酸化力の大きい酸化剤を含有した溶
液を用いて軽くエッチングすることが有効である。この
場合、多孔の凹凸形状を持つ樹脂表面層が溶解除去され
るとともに絶縁膜表面凹部に存在する金属エッチング残
渣（下地導電膜形成時の触媒Ｐｄ及び回路形成後の銅エ
ッチング残り）も除去される結果、導体回路間の線間絶
縁性が向上するとともに、導体回路表面メタライズの際
の導体間めっき析出を抑制できる。ただし、処理時間が
長いと新たに多孔の凹凸形状を持つ樹脂表面層が形成さ
れて導体回路間の線間絶縁性は低下する。On the other hand, as a wet etch, for example,
Chromate, chromate, dichromate, manganate,
It is effective to perform light etching using a solution containing an oxidizing agent having a large oxidizing power such as permanganate. In this case, the resin surface layer having the porous concavo-convex shape is dissolved and removed, and the metal etching residue (catalyst Pd at the time of forming the underlying conductive film and copper etching residue after the circuit is formed) present at the concave portion of the insulating film is also removed. As a result, the insulation between lines between the conductor circuits is improved, and the deposition of plating between conductors at the time of metallizing the surface of the conductor circuit can be suppressed. However, if the processing time is long, a resin surface layer having a porous uneven shape is newly formed, and line insulation between the conductor circuits is reduced.
【００２０】上記導体回路間の絶縁樹脂表面を除去する
方法としては、上記ドライプロセス及びウエットプロセ
スの両方を併用することももちろん可能である。また、
本発明は、層間絶縁膜として感光性樹脂を用いたビルド
アップ法に限らず、層間絶縁膜として熱硬化性樹脂を用
いレーザによってビアホールを形成するビルドアップ法
等、およそ導体回路との接着をとるために絶縁樹脂を粗
化する工程を含むビルドアップ法全てに適用することが
できる。As a method for removing the surface of the insulating resin between the conductor circuits, it is of course possible to use both the dry process and the wet process together. Also,
The present invention is not limited to a build-up method using a photosensitive resin as an interlayer insulating film, and uses a thermosetting resin as an interlayer insulating film to form a via hole by a laser, and the like. Therefore, it can be applied to all the build-up methods including a step of roughening the insulating resin.
【００２１】[0021]
【発明の実施の形態】以下、本発明に係る多層配線基板
の製造方法の一実施例について図面を参照しながら具体
的に説明する。DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS One embodiment of a method for manufacturing a multilayer wiring board according to the present invention will be specifically described below with reference to the drawings.
【００２２】（実施例１）図１（ａ）に示す配線基板１
００として、ガラス布基材にエポキシ樹脂を含浸固化
し、その両面に銅箔を張り合わせた積層板（銅箔厚さ１
８ミクロン）を準備し、銅箔に予め周知の方法により第
一の配線層として回路パターン１０１形成したものを試
料基板とした。(Embodiment 1) Wiring board 1 shown in FIG.
00, a glass cloth substrate was impregnated with epoxy resin and solidified, and copper foil was adhered on both sides of the laminate (copper foil thickness 1).
(8 μm) was prepared, and a circuit board 101 was formed as a first wiring layer on a copper foil in advance by a known method to obtain a sample substrate.
【００２３】次いで、図１（ｂ）に示すように、この配
線基板上に絶縁層１０２をスプレーコータにより塗布形
成した（約５０ミクロン）。用いた絶縁樹脂は、感光性
樹脂組成物で、下記（イ）〜（ハ）と適量の溶剤（エチ
ルセロソルブ）を混合し、８０℃で３０分間加熱撹拌し
た後、常温で他の成分（ニ）〜（チ）を混合して三本ロ
ールにて混練することにより得た。Next, as shown in FIG. 1B, an insulating layer 102 was formed on the wiring substrate by a spray coater (about 50 μm). The insulating resin used is a photosensitive resin composition, which is obtained by mixing the following (a) to (c) with an appropriate amount of a solvent (ethyl cellosolve), heating and stirring at 80 ° C. for 30 minutes, and then stirring other components (d) at room temperature. ) To (H) were mixed and kneaded with a three-roll mill.
【００２４】 （イ）ジアリルフタレート樹脂 １００ｇ （ロ）エポキシ樹脂（エピコート８２８） ３０ｇ （ハ）ペンタエリスリトールトリアクリレート ２０ｇ （ニ）ベンゾインイソプロピルエーテル ４ｇ （ホ）ジシアンジアミド ４ｇ （ヘ）２，４−ジアミノ−６−［２′−メチルイミダゾリル− （１′）］−エチル−ｓ−トリアジン １ｇ （ト）微粒子シリカ ２０ｇ （チ）その他（塗布特性向上のための添加剤） 適量 次に、図１（ｃ）に示すように、ビアホールのパターン
が形成されたネガマスクを介して４００Ｗ高圧水銀ラン
プを用い、２分間ＵＶ光で露光し、現像により所望部に
ビアホール１０３を形成した。(A) diallyl phthalate resin 100 g (B) epoxy resin (Epicoat 828) 30 g (C) pentaerythritol triacrylate 20 g (D) benzoin isopropyl ether 4 g (E) dicyandiamide 4 g (F) 2,4-diamino-6 -[2'-Methylimidazolyl- (1 ')]-ethyl-s-triazine 1 g (g) Fine particle silica 20 g (h) Other (additive for improving coating characteristics) Proper amount Next, FIG. As shown in the drawing, a 400 W high-pressure mercury lamp was used for exposure to UV light for 2 minutes through a negative mask on which a via hole pattern was formed, and a via hole 103 was formed in a desired portion by development.
【００２５】続いて、図１（ｄ）に示すように、絶縁樹
脂層１０２と後工程の下地導電膜との接着強度を確保す
るために、樹脂層１０２の表面粗化処理を行い、粗化面
１０２′を形成した。粗化液は、過マンガン酸カリウム
溶液を用い、この液に１０〜２０分浸漬した後、塩酸ヒ
ドロキシルアミンで、二酸化マンガンを中和した。Subsequently, as shown in FIG. 1D, in order to secure the adhesive strength between the insulating resin layer 102 and the underlying conductive film in a later step, the surface of the resin layer 102 is subjected to a surface roughening treatment. Surface 102 'was formed. As a roughening solution, a potassium permanganate solution was used, immersed in this solution for 10 to 20 minutes, and then manganese dioxide was neutralized with hydroxylamine hydrochloride.
【００２６】さらに、図１（ｅ）に示すように、下地導
電膜１０４をめっき処理で形成する前処理として、基板
の粗化層１０２′をＳｎ，Ｐｄ系の触媒液に浸漬して活
性化し、無電解銅めっきにより下地導電膜１０４を形成
した。その後、基板洗浄による電気銅めっきの前処理工
程を経て、厚付け電気銅めっきを施し、図１（ｆ）に図
示されるめっき導電膜１０５を形成した。Further, as shown in FIG. 1E, as a pretreatment for forming the underlying conductive film 104 by plating, the roughened layer 102 'of the substrate is activated by immersing it in a Sn, Pd-based catalyst solution. The underlying conductive film 104 was formed by electroless copper plating. Thereafter, through a pretreatment step of electrolytic copper plating by washing the substrate, thick copper electroplating was performed to form a plated conductive film 105 shown in FIG. 1 (f).
【００２７】次いで、図１（ｇ）に示すように、選択エ
ッチ法により、下地及びめっき導電膜（１０４，１０
５）の配線パターン化を行った。すなわち、常法により
基板のめっき導電膜１０５上に感光性エッチングドライ
フィルムをラミネートし、所定の回路パターンマスクを
介して露光した後、現像、エッチング、剥離の工程を通
して樹脂上に幅約１００ミクロンの回路（１０４′，１
０５′の二層構造）を形成し、第二の配線層とした。Next, as shown in FIG. 1 (g), the underlayer and the plated conductive films (104, 10) are selectively etched.
The wiring patterning of 5) was performed. That is, a photosensitive etching dry film is laminated on the plating conductive film 105 of the substrate by a conventional method, and is exposed through a predetermined circuit pattern mask. Circuit (104 ', 1
05 ′ (two-layer structure) was formed as a second wiring layer.
【００２８】次に、図１（ｈ）に示すように導体回路を
形成した基板に対し、プラズマアッシングを行った。エ
ッチングガスとしては、酸素を用いた。用いたドライエ
ッチング装置及び処理条件を下記に示す。Next, as shown in FIG. 1H, plasma ashing was performed on the substrate on which the conductor circuit was formed. Oxygen was used as an etching gas. The dry etching apparatus and processing conditions used are shown below.
【００２９】 装置 :Ｏ2プラズマアッシャー(東京応化工業製Ｏ
ＰＭ−ＳＱ1000ＥＷ) Ｏ2流量 :４００ｓｃｃｍ ガス圧 :１３３ｐａ ＲＦパワー:８００Ｗ 処理時間 :２〜３０分 プラズマアッシング後は、絶縁樹脂表面に濃縮された無
機充填剤の残渣層が残るので、図（ｉ）に示すように水
洗を行うことによって残渣層を除去した。水洗は、流水
中で２分行った。Apparatus: O 2 plasma asher (O, manufactured by Tokyo Ohka Kogyo Co., Ltd.)
(PM-SQ1000EW) O 2 flow rate: 400 sccm Gas pressure: 133 pa RF power: 800 W Processing time: 2 to 30 minutes After plasma ashing, a concentrated inorganic filler residue layer remains on the insulating resin surface, and FIG. The residue layer was removed by washing with water as shown in FIG. Washing was performed in running water for 2 minutes.
【００３０】この後、第三の配線層形成に関しても、上
記図１（ｂ）の感光性の絶縁層１０２の形成から図１
（ｇ）の第二配線層を形成する工程までと同様の作業を
行い、第三配線層形成後に最外層絶縁樹脂表面を上記と
同様の条件でプラズマアッシング処理して、最後にソル
ダレジストを塗布、露光、現像することにより三層構造
の多層配線基板を製造した。Thereafter, the formation of the third wiring layer also starts from the formation of the photosensitive insulating layer 102 shown in FIG.
The same operation as in the step (g) of forming the second wiring layer is performed. After the formation of the third wiring layer, the outermost insulating resin surface is subjected to plasma ashing under the same conditions as described above, and finally a solder resist is applied. Exposure and development produced a multilayer wiring board having a three-layer structure.
【００３１】（実施例２）実施例１と同様の感光性絶縁
樹脂を用い、実施例１と同様の工程で多層配線基板を製
造した。実施例１と異なる点は、導体回路形成後の導体
回路間樹脂表面のエッチングとして、ＵＶ／Ｏ3処理を
施したことである。処理条件を下記に示す。Example 2 Using the same photosensitive insulating resin as in Example 1, a multilayer wiring board was manufactured in the same steps as in Example 1. The difference from the first embodiment is that UV / O 3 treatment is performed as etching of the resin surface between the conductor circuits after the formation of the conductor circuits. The processing conditions are shown below.
【００３２】 Ｏ3流量 ：８ＮＬ／ｍｉｎ 一時電流 ：５Ａ 温度 ：１６０±１０℃ ランプからの距離 ：１５ｃｍ 処理時間 ：５〜２０分 実施例１及び実施例２の方法で製造した本発明の多層配
線基板について絶縁特性評価を行った。絶縁特性評価
は、恒温恒湿槽中で５０Ｖの電圧を印可して５００時間
経過後の外層導体回路間（１５０ミクロン）の絶縁抵抗
を測定することで行った。なお、恒温恒湿試験環境は、
温度６５℃、湿度９５％で行った。また、比較のため
に、導体回路形成後に導体回路間樹脂表面に対し、Ｏ2
プラズマ処理及びＵＶ／Ｏ3処理を一切施していない基
板についても同様の測定を行った。O 3 flow rate: 8 NL / min Temporary current: 5 A Temperature: 160 ± 10 ° C. Distance from lamp: 15 cm Processing time: 5 to 20 minutes Multilayer wiring of the present invention manufactured by the method of Example 1 or Example 2 The insulation characteristics of the substrate were evaluated. The insulation characteristics were evaluated by applying a voltage of 50 V in a thermo-hygrostat and measuring the insulation resistance between the outer conductor circuits (150 microns) after 500 hours. The constant temperature and humidity test environment is
The test was performed at a temperature of 65 ° C. and a humidity of 95%. Also, for comparison, O 2 was applied to the resin surface between the conductor circuits after the formation of the conductor circuits.
The same measurement was performed on a substrate that had not been subjected to any plasma treatment or UV / O 3 treatment.
【００３３】実施例１及び実施例２の多層配線基板は、
試験前の初期値が１ｘ１０7メグオーム以上であったの
に対して、恒温恒湿試験５００時間でも１ｘ１０6メグ
オーム以上の抵抗を保持していた。これに対し、導体回
路形成後に導体回路間樹脂表面に対し、Ｏ2プラズマ処
理及びＵＶ／Ｏ3処理を一切施していない場合、恒温恒
湿試験５００時間後の抵抗値が１ｘ１０2オーム以下と
なる基板が発生した。このことから、本発明に係る多層
配線基板は、従来法による基板よりも優れた絶縁特性を
示すことがわかる。The multilayer wiring boards of the first and second embodiments are
While the initial value before the test was 1 × 10 7 megohm or more, the resistance was maintained at 1 × 10 6 megohm or more even in the constant temperature and humidity test for 500 hours. On the other hand, when no O 2 plasma treatment or UV / O 3 treatment is applied to the resin surface between the conductor circuits after the formation of the conductor circuits, the resistance value after 500 hours of the constant temperature and humidity test becomes 1 × 10 2 ohm or less. Substrate occurred. From this, it is understood that the multilayer wiring board according to the present invention exhibits better insulating properties than the board manufactured by the conventional method.
【００３４】（実施例３）実施例１の方法で製造した基
板を使用し、最外層導体回路の表面メタライズとして無
電解ニッケルめっき及び置換金めっきを施した。使用し
ためっき液及びめっき条件は、次の通りである。(Example 3) The substrate manufactured by the method of Example 1 was used, and electroless nickel plating and displacement gold plating were applied as a surface metallization of the outermost conductor circuit. The plating solution and plating conditions used are as follows.
【００３５】 （無電解ニッケルめっき） ＩＣＰニコロンＵ(Ｎｉ−Ｐ) 奧野製薬工業社製 液温 ８５℃ めっき時間 ２０分 （置換金めっき） レクトロレス プレップ 日本エレクトロプレイティング・エンジニヤース 社製 液温 ９０℃ めっき時間 ２０分 無電解ニッケルめっき後及び置換金めっき後に基板表面
を金属顕微鏡にて観察したところ、最外層導体回路間の
もっとも狭い場所（１５０ミクロン）においてもショー
トの発生は認められなかった。これに対して、導体回路
形成後にＯ2プラズマ処理を施していない基板では、ニ
ッケルめっき後に最狭小導体回路間でのショート発生が
認められたことから、本実施例に示す製造法の有効性が
確認できた。(Electroless nickel plating) ICP Nicoron U (Ni-P) manufactured by Okuno Pharmaceutical Co., Ltd. Liquid temperature 85 ° C Plating time 20 minutes (displacement gold plating) Lectroless Prep Liquid temperature 90 ° C manufactured by Nippon Electroplating Engineers The plating time was 20 minutes. After the electroless nickel plating and the displacement gold plating, the surface of the substrate was observed with a metallographic microscope. As a result, no short circuit was observed even in the narrowest portion (150 microns) between the outermost conductor circuits. On the other hand, in the case where the O 2 plasma treatment was not performed after the formation of the conductor circuit, the occurrence of a short circuit between the narrowest conductor circuits after nickel plating was observed. It could be confirmed.
【００３６】（実施例４）実施例２の方法で製造した基
板を使用し、最外層導体回路の表面メタライズとして無
電解ニッケルめっき及び置換金めっきを施した。使用し
ためっき液及びめっき条件は、実施例３に記載の通りで
ある。Example 4 The substrate manufactured by the method of Example 2 was used, and electroless nickel plating and displacement gold plating were applied as surface metallization of the outermost conductor circuit. The plating solution and plating conditions used are as described in Example 3.
【００３７】無電解ニッケルめっき後及び置換金めっき
後に基板表面を金属顕微鏡にて観察したところ、最外層
導体回路間のもっとも狭い場所（１５０ミクロン）にお
いてもショートの発生は認められなかった。When the substrate surface was observed with a metallographic microscope after electroless nickel plating and displacement gold plating, no short circuit was observed even in the narrowest portion (150 microns) between the outermost conductor circuits.
【００３８】（実施例５）実施例１と同様の感光性絶縁
樹脂を用い、実施例１と同様の工程で多層配線基板を製
造した。実施例１と異なる点は、最外層導体回路形成後
の導体回路間樹脂表面のエッチングとして、過マンガン
酸カリウム溶液を用いたことである。処理液の組成及び
処理条件を下記に示す。Example 5 A multilayer wiring board was manufactured using the same photosensitive insulating resin as in Example 1 and in the same process as in Example 1. The difference from the first embodiment is that a potassium permanganate solution is used for etching the resin surface between the conductor circuits after the outermost conductor circuit is formed. The composition of the processing solution and the processing conditions are shown below.
【００３９】 組成 ：過マンガン酸カリウム０．１〜０．５ｍｏｌ／１（リットル） 水酸化ナトリウム ０．２〜０．４ｍｏｌ／１（リットル） 液温 ：５０〜９０℃ 処理時間３〜５分 本方法で製造した基板を使用し、最外層導体回路の表面
メタライズとして無電解ニッケルめっき及び置換金めっ
きを施した。使用しためっき液及びめっき条件は、実施
例３に記載の通りである。Composition: potassium permanganate 0.1 to 0.5 mol / 1 (liter) Sodium hydroxide 0.2 to 0.4 mol / 1 (liter) Liquid temperature: 50 to 90 ° C. Treatment time 3 to 5 minutes Using the substrate manufactured by the method, electroless nickel plating and displacement gold plating were applied as surface metallization of the outermost conductor circuit. The plating solution and plating conditions used are as described in Example 3.
【００４０】無電解ニッケルめっき後及び置換金めっき
後に基板表面を金属顕微鏡にて観察したところ、最外層
導体回路間のもっとも狭い場所（１５０ミクロン）にお
いてもショートの発生は認められなかった。When the surface of the substrate was observed with a metallographic microscope after electroless nickel plating and displacement gold plating, no short circuit was observed even in the narrowest portion (150 microns) between the outermost conductor circuits.
【００４１】[0041]
【発明の効果】以上詳述したように、本発明によれば、
導体回路間の線間絶縁特性に優れた、信頼性の高いビル
ドアップ多層配線基板を容易に製造することができる。
さらに、本発明によれば、最表面導体回路間隔が狭い場
合でもめっき導体回路間へのめっき異常析出がなく、高
歩留まりで表面メタライズが可能なビルドアップ基板を
製造できる。As described in detail above, according to the present invention,
A highly reliable build-up multilayer wiring board having excellent line insulation characteristics between conductor circuits can be easily manufactured.
Further, according to the present invention, a build-up substrate capable of performing high-yield surface metallization with no abnormal deposition of plating between the plated conductor circuits even when the interval between the outermost conductor circuits is small can be manufactured.
【図１】実施例１の多層配線基板の製造工程を示す断面
図。FIG. 1 is a sectional view showing a manufacturing process of a multilayer wiring board according to a first embodiment.
【図２】実施例１の多層配線基板の製造工程を示す流れ
図。FIG. 2 is a flowchart showing a manufacturing process of the multilayer wiring board according to the first embodiment.
【図３】実施例２の多層配線基板の製造工程を示す流れ
図。FIG. 3 is a flowchart showing a manufacturing process of the multilayer wiring board according to the second embodiment.
【図４】実施例５の多層配線基板の製造工程を示す流れ
図。FIG. 4 is a flowchart showing a manufacturing process of a multilayer wiring board according to a fifth embodiment.
１００…配線基板、 １０１…回路パターン、 １
０２…絶縁層、１０２′…粗化層、 １０３…ビヤ
ホール、 １０４…下地導電膜、１０４′…回路パタ
ーン、１０５…めっき導電膜、 １０５′…回路パター
ン、１０６…回路パターンの間隙 １０７…無機充
填剤の濃縮残渣層。100: wiring board, 101: circuit pattern, 1
02: insulating layer, 102 ': roughened layer, 103: via hole, 104: base conductive film, 104': circuit pattern, 105: plated conductive film, 105 ': circuit pattern, 106: gap between circuit patterns 107: inorganic filling Concentrated residue layer of the agent.
───────────────────────────────────────────────────── フロントページの続き (72)発明者 渡部 真貴雄 神奈川県横浜市戸塚区戸塚町216番地株式 会社日立製作所情報通信事業部内 ──────────────────────────────────────────────────続 き Continued on the front page (72) Inventor Makio Watanabe 216 Totsukacho, Totsuka-ku, Yokohama-shi, Kanagawa Pref.
Claims (8)
を交互に繰り返し、ビルドアップ方式により多層配線基
板を製造する方法において、導体回路形成後に導体回路
間の絶縁樹脂表面をエッチングにより除去する工程を含
む多層配線基板の製造方法。In a method of manufacturing a multilayer wiring board by a build-up method by alternately repeating a conductive circuit forming step and an interlayer insulating film forming step, an insulating resin surface between the conductive circuits is removed by etching after forming the conductive circuits. A method for manufacturing a multilayer wiring board including steps.
する工程が、ドライプロセスを用いて有機成分を除去す
るとともに樹脂表面の無機成分を濃縮する工程と、水洗
によって上記濃縮無機成分を除去する工程とから成るこ
とを特徴とする請求項１記載の多層配線基板の製造方
法。2. The step of removing the surface of the insulating resin by etching includes the steps of removing an organic component using a dry process and concentrating an inorganic component on the resin surface, and a step of removing the concentrated inorganic component by washing with water. 2. The method for manufacturing a multilayer wiring board according to claim 1, comprising:
用いた請求項２記載の多層配線基板の製造方法。3. The method for manufacturing a multilayer wiring board according to claim 2 , wherein O 2 plasma is used as said dry process.
いた請求項２記載の多層配線基板の製造方法。4. The method for manufacturing a multilayer wiring board according to claim 2, wherein UV / O 3 is used as said dry process.
する方法として酸化力の大きな酸化剤を含有する溶液を
用い、絶縁樹脂表面を軽くエッチング処理した後、中和
処理する工程を通すことを特徴とする請求項１記載の多
層配線基板の製造方法。5. A method for etching an insulating resin surface according to claim 1, wherein a solution containing an oxidizing agent having a large oxidizing power is passed through a step of lightly etching the insulating resin surface and then neutralizing. 2. The method for manufacturing a multilayer wiring board according to claim 1, wherein:
クロム酸塩、重クロム酸塩、マンガン酸塩、過マンガン
酸塩のいずれかから成る請求項５記載の多層配線基板の
製造方法。6. The oxidizing agent having a large oxidizing power is chromic acid,
6. The method for producing a multilayer wiring board according to claim 5, comprising a chromate, a dichromate, a manganate, or a permanganate.
室温で固形の多官能不飽和化合物、エポキシ樹脂、アク
リレートモノマー、光重合開始剤、アミン系の熱硬化剤
及び無機充填剤から成る感光性絶縁樹脂組成物で構成し
て成る多層配線基板の製造方法。7. A photosensitive material comprising the interlayer insulating film according to claim 1 comprising a polyfunctional unsaturated compound which is solid at least at room temperature, an epoxy resin, an acrylate monomer, a photopolymerization initiator, an amine-based thermosetting agent and an inorganic filler. A method for producing a multilayer wiring board comprising a conductive insulating resin composition.
不飽和基を付加反応させた２官能以上の多官能固形エポ
キシ樹脂、アクリレートモノマー、光重合開始剤、アミ
ン系の熱硬化剤及び無機充填剤から成る感光性絶縁樹脂
組成物で構成して成る多層配線基板の製造方法。8. An interlayer insulating film according to claim 1, wherein a bifunctional or higher polyfunctional solid epoxy resin obtained by subjecting at least an unsaturated group to addition reaction, an acrylate monomer, a photopolymerization initiator, an amine-based thermosetting agent, and an inorganic material. A method for producing a multilayer wiring board comprising a photosensitive insulating resin composition comprising a filler.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP18945697A JPH1140951A (en) | 1997-07-15 | 1997-07-15 | Manufacture of multilayred wiring board |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP18945697A JPH1140951A (en) | 1997-07-15 | 1997-07-15 | Manufacture of multilayred wiring board |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH1140951A true JPH1140951A (en) | 1999-02-12 |
Family
ID=16241572
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP18945697A Pending JPH1140951A (en) | 1997-07-15 | 1997-07-15 | Manufacture of multilayred wiring board |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH1140951A (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2006060149A (en) * | 2004-08-23 | 2006-03-02 | Fuji Photo Film Co Ltd | Manufacturing method of maultilayer wiring board |
| JP2006344920A (en) * | 2005-05-10 | 2006-12-21 | Hitachi Chem Co Ltd | Printed circuit board, manufacturing method therefor, semiconductor chip mounting substrate, manufacturing method therefor, and semiconductor package |
| CN102633112A (en) * | 2012-04-19 | 2012-08-15 | 德清明裕照明电器有限公司 | Driving mechanism of feeding plate |
-
1997
- 1997-07-15 JP JP18945697A patent/JPH1140951A/en active Pending
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2006060149A (en) * | 2004-08-23 | 2006-03-02 | Fuji Photo Film Co Ltd | Manufacturing method of maultilayer wiring board |
| JP4505284B2 (en) * | 2004-08-23 | 2010-07-21 | 富士フイルム株式会社 | Manufacturing method of multilayer wiring board |
| JP2006344920A (en) * | 2005-05-10 | 2006-12-21 | Hitachi Chem Co Ltd | Printed circuit board, manufacturing method therefor, semiconductor chip mounting substrate, manufacturing method therefor, and semiconductor package |
| CN102633112A (en) * | 2012-04-19 | 2012-08-15 | 德清明裕照明电器有限公司 | Driving mechanism of feeding plate |
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