JPH118264A - 半導体装置及びその製造方法 - Google Patents
半導体装置及びその製造方法Info
- Publication number
- JPH118264A JPH118264A JP9156985A JP15698597A JPH118264A JP H118264 A JPH118264 A JP H118264A JP 9156985 A JP9156985 A JP 9156985A JP 15698597 A JP15698597 A JP 15698597A JP H118264 A JPH118264 A JP H118264A
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- Prior art keywords
- pad electrode
- insulating film
- interlayer insulating
- semiconductor device
- pad
- Prior art date
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- H01L24/02—Bonding areas ; Manufacturing methods related thereto
- H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
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Abstract
もパッドと絶縁膜の密着力が低下することのないパッド
電極を持つ半導体装置及びその製造方法を提供する。 【解決手段】 半導体回路素子が形成されている半導体
基板1上に外部との接続のためのパッド電極3a、3b
が設けられている半導体装置において、前記パッド電極
3a、3bとその下層の層間絶縁膜2との界面が凹凸で
あることを特徴とする。
Description
し、特に外部との接続に用いるパッド電極の構造及び製
造方法に関する。
に示すように、半導体基板1上にSiO2等の絶縁膜2
が形成され、かつその絶縁膜上にAl等で形成されたパ
ッド電極3が形成されており、さらにそのパッド電極3
の一部を覆うように半導体素子の保護のためのパッシベ
ーション膜4が形成されていた。
が薄い場合パッド電極の厚みを確保するため図8のよう
に最上層の配線層のみでなくその下層の配線層でパッド
電極3aを形成した後、配線層間の絶縁膜2のパッド電
極3a上に開口を設け、さらにパッド電極3bを形成後
パッシベーション膜4を形成する場合もある。
ようなものである。
絶縁膜2上にAl等をスパッタ法などにより全面に形成
し、その後フォトリソグラフィー及びエッチング法を用
いて所望の形状の配線層及び電気接続を行うためのパッ
ド電極3を選択的に形成する(図9a)。
面にシリコンの酸化物または窒化物等のパッシベーショ
ン膜を形成し、さらにパッド電極上のみをパッド電極同
様に選択的にエッチングし開口を設け(図9b)る事に
より形成していた。
ーション膜の代わりにSiO2等の層間絶縁膜2を形成
し、さらにその上部の配線を形成すると同時にパッド電
極3bを形成した後(図9c)、さらにパッシベーショ
ン膜を形成する事により形成していた(図9d)。
の後金線等のワイヤを用いたワイヤボンディング法やフ
ィルムキャリアを用いたTABボンディング法等により
外部と接続される。
用した熱圧着法である。
ディングでの状態を示す。
に金線6aが通されており、この金線を放電により溶解
させて金ボール6bを形成し加熱及び加圧をしながら半
導体装置状のパッド電極3に圧着を行うがその際キャピ
ラリに超音波振動を与える事によりパッド電極3と金ボ
ール6bの接合をより安定的に行っている。
ルの接合は行われるものの図10のように、パッド電極
3とその下層の絶縁膜2との界面が平滑な面であるた
め、ボンディングの際に印可される超音波振動によって
界面で滑りが起こり、パッド電極3と絶縁層2の界面の
密着強度を弱くしてしまいその界面でのはがれが発生し
やすくなり、初期的にはがれて接続部が電気的にオープ
ンとなるため歩留が低下したり使用中の温度変化などに
よる応力によりはがれが発生し、信頼性を低下させる原
因となる。
幅が狭くまた配線の厚みが薄くなる中で多層配線のため
の層間の絶縁膜の平坦化技術が進んでいるため、ボンデ
ィングの際に印可される超音波振動がパッド電極と絶縁
膜2の界面の密着力を低下させる事が大きな問題となっ
てきている。
あり、ボンディングの際の超音波振動が印可されてもパ
ッドと絶縁膜の密着力が低下することのないパッド電極
を持つ半導体装置及びその製造方法を提供することを目
的とする。
によって達成される。
成されている半導体基板上に外部との接続のためのパッ
ド電極が設けられている半導体装置において、前記パッ
ド電極とその下層の層間絶縁膜との界面が凹凸であるこ
とを特徴とする半導体装置を提案するものであり、前記
凹凸はその凹部面積がパッドの面積の10%以上であ
り、かつ凹部と凸部の段差が300オングストローム〜
3000オングストロームであることを含む。また本発
明は、半導体素子を形成した半導体基板上に層間絶縁膜
を形成する工程と層間絶縁膜上のパッド電極が形成され
る部分に選択的にもしくは層間絶縁膜全面に凹凸を形成
する工程とパッド電極を形成する工程とを少なくとも有
することを特徴とする半導体装置の製造方法を提案する
ものであり、凹凸を層間絶縁膜を選択的にエッチングす
ることにより形成すること、層間絶縁膜に選択的に凹凸
を設けた後に凹凸に金属を埋め込む工程を含むことを含
む。
図面を参照して説明する。
図である。
成され、そのパッド3a上に形成された層間絶縁膜2に
マトリックス状に形成された開口8が形成されており、
かつその開口の内部に金属層9が層間膜2よりも低い高
さで形成されている。
る金属層9とにより凹凸が形成され、その凹凸のさらに
上部にパッド電極3b及びパッシベーション膜4が形成
されている。
ンディング時における形態を示す断面図である。
ール6bとパッド電極3bとの間で両者の変形に寄与す
ると共にさらにその下層のパッド電極3bと層間絶縁膜
2の間にも伝達されるが、その界面が凹凸により一平面
上にないため滑りを起こすことがない。
の間の密着強度が低下させることなくボンディングを行
うことができる。
のパッド電極と層間絶縁膜2との界面が一平面上に存在
し、かつその方向とボンディングの際に印可される超音
波振動の方向とが一致することにより密着性が低下する
ことに着目し、パッド電極と層間絶縁膜の界面が一平面
ではなく凹凸を設けることによりパッド電極と層間絶縁
膜の界面で滑りが起こることを防止するためパッド電極
と層間絶縁膜間の密着力の低下が発生しないため、歩留
及び信頼性の高い半導体装置を提供することができる。
する。
使用し、また、開口の大きさは径0.5μmのものを1
ミクロン間隔で形成して金属層にタングステンを使用し
た。
μmに形成し、その上部にさらにパッド電極を形成して
いる。
する。
面に形成しフォトリソグラフィーにより選択的にパッド
電極を形成する(図4a)。
間絶縁膜であるSiO2をプラズマCVD法により形成
する(図4b)。
選択的にパッド上部に開口を設けさらに開口を含む半導
体基板全面にCVD法によりタングステン層を形成する
(図4c)。
事により層間絶縁膜の開口内にタングステンを残す。こ
のときタングステン層が層間絶縁膜上に残らないように
するためエッチバックをややオーバーさせるため層間絶
縁膜とタングステンの間に約0.1μm程度の段差即ち
凹凸が形成される(図4d)。
極と同様の方法にて形成し(図4e)た後、パッド電極
を含む半導体基板全面にSiN等のパッシベーション膜
を形成し、パッド電極上部を選択的にエッチング除去し
て完成する(図4f)。
なく直接凹凸を形成したものであり図2a、b及び図3
a、bに示すとおりである。
導体基板(図5a)上の層間絶縁膜を選択的にエッチン
グして凹部10を形成する(図5b)。
5c)パッシベーション膜または層間絶縁膜を形成し
(図5d、図2b)、必要な場合はさらにパッド電極を
上部に形成(図5e)、パッシベーション膜を形成する
(図5f、図3b)。
としたが0.03μm以上の深さで形成しても問題はな
い。ただし、深くするためには層間絶縁膜を厚くするこ
とになるため0.3μm程度までが現実的である。
が矩形等の形状でもよく、またその数についても凹部が
パッドの面積の10%以上であれば効果が得られる。
ンディング法を用いて説明したがAl線やTABを用い
たボンディングであっても、超音波振動を印可するボン
ディング法であれば同様の効果が得られることはいうま
でもない。
し垂直に形成したが開口の断面形状はテーパー状であっ
ても効果が得られる。
角度により効果の大きさに差が生じるため可能な限り角
度は大きくする方がよい。
低下による初期的なボンディング不良が発生しないこと
である。
密着強度の低下がないため長期的な使用にも耐えうる信
頼性を確保できることである。
外地平面で構成されず、凹凸を有している構造となって
いるため、ボンディングの際に印可される超音波振動が
パッド電極と層間絶縁膜の界面で滑りを発生させること
がないからである。
あり、図1(b)は図1(a)の断面図である。
示す平面図であり、図2(b)は図2(a)の断面図で
ある。
例を示す平面図であり、図3(b)は図3(a)の断面
図である。
断面図である。
断面図である。
る。
り、図7(b)は図7(a)の断面図である。
す平面図であり、図8(b)は図8(a)の断面図であ
る。
面図である。
る。
Claims (5)
- 【請求項1】 半導体回路素子が形成されている半導体
基板上に外部との接続のためのパッド電極が設けられて
いる半導体装置において、前記パッド電極とその下層の
層間絶縁膜との界面が凹凸であることを特徴とする半導
体装置。 - 【請求項2】 前記凹凸はその凹部面積がパッドの面積
の10%以上であり、かつ凹部と凸部の段差が300オ
ングストローム〜3000オングストロームである請求
項1に記載の半導体装置。 - 【請求項3】 半導体素子を形成した半導体基板上に層
間絶縁膜を形成する工程と層間絶縁膜上のパッド電極が
形成される部分に選択的もしくは層間絶縁膜全面に凹凸
を形成する工程とパッド電極を形成する工程とを少なく
とも有することを特徴とする半導体装置の製造方法。 - 【請求項4】 凹凸を層間絶縁膜を選択的にエッチング
することにより形成する請求項3に記載の半導体装置の
製造方法。 - 【請求項5】 層間絶縁膜に選択的に凹凸を設けた後に
凹凸に金属を埋め込む工程を含む請求項4に記載の半導
体装置の製造方法。
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP9156985A JP2964999B2 (ja) | 1997-06-13 | 1997-06-13 | 半導体装置及びその製造方法 |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP9156985A JP2964999B2 (ja) | 1997-06-13 | 1997-06-13 | 半導体装置及びその製造方法 |
Publications (2)
Publication Number | Publication Date |
---|---|
JPH118264A true JPH118264A (ja) | 1999-01-12 |
JP2964999B2 JP2964999B2 (ja) | 1999-10-18 |
Family
ID=15639661
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP9156985A Expired - Fee Related JP2964999B2 (ja) | 1997-06-13 | 1997-06-13 | 半導体装置及びその製造方法 |
Country Status (1)
Country | Link |
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JP (1) | JP2964999B2 (ja) |
Cited By (8)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6417568B1 (en) | 1999-03-12 | 2002-07-09 | Nec Corporation | Semiconductor device |
JP2002289640A (ja) * | 2001-03-27 | 2002-10-04 | Hitachi Chem Co Ltd | ワイヤボンディング接続電極構造 |
WO2003001595A3 (en) * | 2001-06-25 | 2004-05-27 | Koninkl Philips Electronics Nv | Electronic device |
EP1519411A2 (en) * | 2003-09-26 | 2005-03-30 | Matsushita Electric Industrial Co., Ltd. | Semiconductor device and method for fabricating the same |
JP2005136270A (ja) * | 2003-10-31 | 2005-05-26 | Nec Kansai Ltd | 縦型mosfetを備えた半導体装置 |
JP2006165515A (ja) * | 2004-11-11 | 2006-06-22 | Denso Corp | 半導体装置およびその製造方法 |
JP2007227556A (ja) * | 2006-02-22 | 2007-09-06 | Nec Electronics Corp | 半導体装置 |
US8346024B2 (en) | 2005-07-05 | 2013-01-01 | Silverbrook Research Pty Ltd | Method of initiating requested action via substrate printed with naphthalocyanine dye |
Families Citing this family (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP3425582B2 (ja) | 2000-04-14 | 2003-07-14 | Necエレクトロニクス株式会社 | 半導体装置及びその製造方法 |
JP2017045910A (ja) | 2015-08-28 | 2017-03-02 | ルネサスエレクトロニクス株式会社 | 半導体装置および半導体装置の製造方法 |
-
1997
- 1997-06-13 JP JP9156985A patent/JP2964999B2/ja not_active Expired - Fee Related
Cited By (11)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6417568B1 (en) | 1999-03-12 | 2002-07-09 | Nec Corporation | Semiconductor device |
JP2002289640A (ja) * | 2001-03-27 | 2002-10-04 | Hitachi Chem Co Ltd | ワイヤボンディング接続電極構造 |
WO2003001595A3 (en) * | 2001-06-25 | 2004-05-27 | Koninkl Philips Electronics Nv | Electronic device |
EP1519411A2 (en) * | 2003-09-26 | 2005-03-30 | Matsushita Electric Industrial Co., Ltd. | Semiconductor device and method for fabricating the same |
EP1519411A3 (en) * | 2003-09-26 | 2010-01-13 | Panasonic Corporation | Semiconductor device and method for fabricating the same |
US7741207B2 (en) | 2003-09-26 | 2010-06-22 | Panasonic Corporation | Semiconductor device with multilayered metal pattern |
JP2005136270A (ja) * | 2003-10-31 | 2005-05-26 | Nec Kansai Ltd | 縦型mosfetを備えた半導体装置 |
JP2006165515A (ja) * | 2004-11-11 | 2006-06-22 | Denso Corp | 半導体装置およびその製造方法 |
JP4674522B2 (ja) * | 2004-11-11 | 2011-04-20 | 株式会社デンソー | 半導体装置 |
US8346024B2 (en) | 2005-07-05 | 2013-01-01 | Silverbrook Research Pty Ltd | Method of initiating requested action via substrate printed with naphthalocyanine dye |
JP2007227556A (ja) * | 2006-02-22 | 2007-09-06 | Nec Electronics Corp | 半導体装置 |
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