JP4674522B2 - 半導体装置 - Google Patents
半導体装置 Download PDFInfo
- Publication number
- JP4674522B2 JP4674522B2 JP2005298076A JP2005298076A JP4674522B2 JP 4674522 B2 JP4674522 B2 JP 4674522B2 JP 2005298076 A JP2005298076 A JP 2005298076A JP 2005298076 A JP2005298076 A JP 2005298076A JP 4674522 B2 JP4674522 B2 JP 4674522B2
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- film
- semiconductor device
- electrode
- thick
- protective film
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Description
特に、前記厚膜電極の表面窪みの底面が前記衝撃吸収梁である層間保護膜の表面より高くなるよう前記厚膜電極の膜厚を設定することにより、前記厚膜電極へのボンディング接続を実施した際のボンディング衝撃を、前記アルミ膜またはアルミ合金膜からなる被覆層,前期厚膜電極および、前記衝撃吸収梁とで緩和・吸収することができる。
(第1の実施形態)
図1(a)は本発明の第1の実施例による半導体装置H1を模式的に示す図である。また、図1(b)は、図1(a)の破線で囲ったA部の拡大図で、第1の実施例の作用を示す図である。
図2(a),(b)に示す開口部5ka,5kbは、図3(a),(b)に示す開口部5kc,5kdに較べて、開口部全体の開口面積が大きいために接触抵抗をより低減することができる。
以下、図1(a)に示す半導体装置H1の製造方法について、図5から図7を参照して説明する。
次に、図6(a)に示すように、前記層間保護膜5上に、前記集電電極4に接続するため、厚膜電極6となる前記集電電極と同一材料の金属膜を複数の開口部5kを介して形成する。厚膜電極6となる金属膜の材質としては、アルミまたはアルミ合金が望ましい。
(第2の実施形態)
図8は本発明の第2の実施例による半導体装置H2を模式的に示す図である。
図8に示す本発明による半導体装置H2も、第1実施形態の半導体装置H1と同様に、複数のパワ−素子ユニットセルがシリコン基板1の表層部に配置された半導体装置である。尚、図8の半導体装置H2において、集電電極4より下層の構造は図1(a)の半導体装置H1と同様であり、その説明は省略する。
(第3の実施形態)
図10(a)は、本実施形態における半導体装置H3の模式的な断面構造を示す図である。図10(b)は、図10(a)の破線で囲ったB部の拡大図で、本発明の作用効果を説明する図である。
(第4の実施形態)
図17は本発明の第4の実施例による半導体装置D1を模式的に示す図である。
(第5の実施形態)
図18は本発明の第5の実施例による半導体装置D2を模式的に示す図である。
(第6の実施形態)
図19は本発明の第6の実施例による半導体装置D3を模式的に示す図である。
図19の半導体装置D3においても、衝撃吸収梁30hが上部電極15と厚いパッド電極20とで包み込まれた構造となっている。従って、半導体装置D3のボンディング接続時の作用と効果については、図11の半導体装置H4と同様であるため詳細は省略する。また製造方法についても上層電極15の形成後は図11の半導体装置H4と同様であるため、半導体装置D3の製造方法の一例は、図12に示す製造方法と同様のためその詳細は省略する。
(第7の実施形態)
図20は本発明の第7の実施例による半導体装置L1を模式的に示す図である。
(第8の実施形態)
図21は本発明の第8の実施例による半導体装置L2を模式的に示す図である。
(第9の実施形態)
図22は本発明の第9の実施例による半導体装置L3を模式的に示す図である。
と同様にして、厚いパッド電極40を被覆する最終保護樹脂膜35が半導体基板上の最表面に形成され、厚いパッド電極40へボンディングワイヤ36を接続するために、複数個の衝撃吸収梁70hの上方において、最終保護樹脂膜35が開口されている。従って、第1のバリア層40a,厚いパッド電極400,第2のバリア層40bおよび,最終保護樹脂膜35の望ましい材質および構造は、図11の半導体装置H4および図19の半導体装置D3と同様の材質および構造であるため、その詳細は省略する。
1 シリコン基板
2 引き出し配線
3 層間絶縁層
4 集電電極
5,50 層間保護膜
50a 下層誘電体層
50b 上層誘電体層
5k,5ka〜5kd,50k 開口部
5Ca,5Cb コーナー
5h,5ha〜5hd,50h,16h,30h,33h,70h,80h 衝撃吸収梁
6,60,61 厚膜電極
60a,20a,40a,90a 第1のバリア層
60b,20b,40b,90b 第2のバリア層
60c,20c,40c,90c アルミニウム膜またはアルミニウム合金膜
7 最終保護膜
9,19,36,88 ボンディングワイヤ
10 縦型素子のユニットセル
11 複数の縦型素子が形成された基板
12 裏面電極
13 制御電極
14 絶縁層
15 表面電極
16,30,33,70,80 保護膜
17 厚い表面電極
18,35,87 最終保護樹脂膜
20,40,90 厚いパッド電極
30a,70a,80a 下層保護膜
30b,70b,80b 上層保護膜
31,81 集積回路が形成された半導体基板
32 第1のパッド電極
34 第2のパッド電極
41,82 パッド電極
84 厚い電極膜
83,85,86 マスク材
Claims (12)
- 半導体基板に複数のパワ−MOSセルを配置し、
前記複数のパワ−MOSセル上において、
前記パワ−MOSセルのソ−ス,ドレインそれぞれに対し、コンタクト孔を介して接続し電位を引き出すための引き出し配線が配置され、
ソ−ス,ドレインそれぞれの複数の前記引き出し配線を、ヴィア孔を介して並列接続することにより集電するための集電電極が配置され、
ソ−ス,ドレインそれぞれの前記集電電極上に形成した層間保護膜に、開口部間が梁状となるように形成した複数の開口部が設けられ、
前記開口部においてソ−ス,ドレインそれぞれの前記集電電極と第1のバリア層を介して接続された、前記集電電極を構成している材料より機械的強度の高い材料で構成された厚膜電極が設けられ、
前記厚膜電極の上面および全側面を、第2のバリア層を介してアルミ膜またはアルミ合金膜により被覆し、
ボンディング接続を行うのに必要な領域を開口した最終保護膜で前記厚膜電極を被覆した構造の半導体装置。 - 前記開口部は、コ−ナ−が丸めまたは面取りした平面構造であることを特徴とする請求項1に記載の半導体装置。
- 前記開口部は、1辺が他辺より長い開口部であり、
前記開口部の長い辺が、ボンディング接続時の超音波振動の振動方向と直交するよう配置されることを特徴とする請求項1または2に記載の半導体装置。 - 前記厚膜電極の膜厚は、前記開口部に起因する表面の窪み底部が前記層間保護膜の表面より上部に位置する膜厚であることを特徴とする請求項1乃至3のいずれか一項に記載の半導体装置。
- 前記集電電極の材質が、アルミまたはアルミ合金であることを特徴とする請求項1乃至4のいずれか一項に記載の半導体装置。
- 前記第1のバリア層として、チタン,チタン窒化物,チタンタングステン,またはそれらの積層膜を用いたことを特徴とする請求項1乃至5のいずれか一項に記載の半導体装置。
- 前記厚膜電極の材質が、銅であることを特徴とする請求項1乃至6のいずれか一項に記載の半導体装置。
- 前記第2のバリア層として、チタン,チタン窒化物,チタンタングステン,またはそれらの積層膜を用いたことを特徴とする請求項1乃至7のいずれか一項に記載の半導体装置。
- 前記最終保護膜は、ポリイミド樹脂膜であり、その膜厚が前記厚膜電極の膜厚より厚いことを特徴とする請求項1乃至8のいずれか一項に記載の半導体装置。
- 前記層間保護膜における開口部の端面の断面形状が、テーパー形状であり、
前記厚膜電極の前記開口部に起因する表面窪みが、緩やかなテーパー形状となることを特徴とする請求項1乃至9のいずれか一項に記載の半導体装置。 - 前記層間保護膜は、シリコン酸化膜とシリコン窒化膜を積層した2層膜であることを特徴とする請求項10に記載の半導体装置。
- 前記厚膜電極の表面窪み部のテーパー角が、基板面の垂線を基準として、45度以上のテーパー角であることを特徴とする請求項10または11に記載の半導体装置。
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JP2005298076A JP4674522B2 (ja) | 2004-11-11 | 2005-10-12 | 半導体装置 |
IT002124A ITMI20052124A1 (it) | 2004-11-11 | 2005-11-08 | Dispositivo a semiconduttori di tipo ad integrazione e metodo di fabbricazione dello stesso |
US11/270,458 US7420283B2 (en) | 2004-11-11 | 2005-11-10 | Integration type semiconductor device and method for manufacturing the same |
US12/213,259 US7579695B2 (en) | 2004-11-11 | 2008-06-17 | Integration type semiconductor device and method for manufacturing the same |
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