JPH11142878A - Formation of display transistor array panel - Google Patents

Formation of display transistor array panel

Info

Publication number
JPH11142878A
JPH11142878A JP9310299A JP31029997A JPH11142878A JP H11142878 A JPH11142878 A JP H11142878A JP 9310299 A JP9310299 A JP 9310299A JP 31029997 A JP31029997 A JP 31029997A JP H11142878 A JPH11142878 A JP H11142878A
Authority
JP
Japan
Prior art keywords
substrate
forming
transistor array
array panel
display
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP9310299A
Other languages
Japanese (ja)
Other versions
JP3406207B2 (en
Inventor
Masabumi Shimizu
正文 清水
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Sharp Corp
Original Assignee
Sharp Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sharp Corp filed Critical Sharp Corp
Priority to JP31029997A priority Critical patent/JP3406207B2/en
Publication of JPH11142878A publication Critical patent/JPH11142878A/en
Application granted granted Critical
Publication of JP3406207B2 publication Critical patent/JP3406207B2/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/683—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L21/6835—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/13613—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit the semiconductor element being formed on a first substrate and thereafter transferred to the final cell substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2221/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
    • H01L2221/67—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere
    • H01L2221/683—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L2221/68304—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
    • H01L2221/68368—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support used in a transfer process involving at least two transfer steps, i.e. including an intermediate handle substrate

Abstract

PROBLEM TO BE SOLVED: To sharply reduce a manufacturing cost. SOLUTION: Plural TFT elements 43 are formed on a 1st substrate consisting of a Si substrate at pitches dx/m, dy/n with respective element separation grooves 44 intervened. The dx and dy are array pitches of pixels and each of (m) and (n) is a natural number of >=2. A 2nd substrate 45 is stuck to the 1st substrate with UV peeling resin 46, and after removing the 1st substrate by etching, respective TFT elements 43 are separated. Only TFT elements 43 to be transferred are selectively stuck with adhesive resin 51, and selectively irradiated with ultraviolet rays 62 from the side of the 2nd substrate 45 to selectively be transferred to a 3rd substrate 47. Thus, the same selected TFT element 43 can be transferred to (m×n) pieces of panel substrates 47 while forming (m×n) times as many as a necessary number of TFT elements 43 on one piece of 2nd substrate 45, so that cost required for forming TFT elements 43 on the 1st substrate can be reduced approximately to become 1/(m×n).

Description

【発明の詳細な説明】DETAILED DESCRIPTION OF THE INVENTION

【０００１】[0001]

【発明の属する技術分野】この発明は、薄膜トランジス
タ(以下、ＴＦＴと言う)等のスイッチング素子を有し
て、ディスプレイに使用される表示用トランジスタアレ
イパネルに関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a display transistor array panel having a switching element such as a thin film transistor (hereinafter, referred to as a TFT) and used for a display.

【０００２】[0002]

【従来の技術】従来、コンピュータやテレビジョン装置
等のディスプレイに使用される表示用トランジスタアレ
イパネルの形成方法として、特開平１−３８７２７号公
報(以下、従来例１と言う)やＵＳＰ５４３８２４１(以
下、従来例２と言う)に開示されているようなものがあ
る。この表示用トランジスタアレイパネルの形成方法で
は、シリコン単結晶基板上に単結晶シリコンのＴＦＴア
レイを形成し、これを別のパネル用ガラスあるいは透明
有機フィルム基板に転写して表示用トランジスタアレイ
パネルを得ている。2. Description of the Related Art Conventionally, as a method of forming a transistor array panel for display used in a display of a computer or a television device, Japanese Patent Application Laid-Open No. 1-38727 (hereinafter referred to as Conventional Example 1) and US Pat. Conventional example 2) is disclosed. In this method of forming a display transistor array panel, a TFT array of single crystal silicon is formed on a silicon single crystal substrate, and the TFT array is transferred to another panel glass or transparent organic film substrate to obtain a display transistor array panel. ing.

【０００３】上記従来例１では、単結晶シリコン薄膜に
ＴＦＴアレイおよび周辺回路を形成し、ガラス基板上に
この単結晶シリコン薄膜の各辺を互いに密着させて複数
枚を平面的に敷き詰めて広い画面を得ている。また、従
来例２では、ＳＯＩ技術を使用して第１の基板上に酸化
物層を介して薄いシリコン単結晶フィルムを形成し、こ
のシリコン単結晶フィルム上にＴＦＴアレイを作成す
る。続いて、このＴＦＴアレイをガラス等の第２の透明
絶縁基板上に転写し、上記シリコン単結晶フィルムが形
成された上記基板全体を除去することで第１の転写プロ
セスを完了する。また、必要な場合には第２の転写プロ
セスに移行し、第３のディスプレイパネル基板に転写し
て表示用ＴＦＴアレイパネルとしている。In the above prior art example 1, a TFT array and peripheral circuits are formed on a single crystal silicon thin film, and the sides of the single crystal silicon thin film are brought into close contact with each other on a glass substrate, and a plurality of the single crystal silicon thin films are laid flat to form a wide screen. Have gained. In Conventional Example 2, a thin silicon single crystal film is formed on a first substrate via an oxide layer using the SOI technique, and a TFT array is formed on the silicon single crystal film. Subsequently, the TFT array is transferred onto a second transparent insulating substrate such as glass, and the entire substrate on which the silicon single crystal film is formed is removed to complete the first transfer process. If necessary, the process shifts to the second transfer process, and the image is transferred to a third display panel substrate to form a display TFT array panel.

【０００４】ここで、上記シリコン単結晶フィルムが形
成された基板全体を除去する方法には、図１０に示すよ
うな基板とディバイスとの間に剥離層を設けエッチング
によって剥離層を除去する方法、あるいは、図１１に示
すような基板全体をエッチバック工程によってエッチ除
去する方法がある。Here, a method of removing the entire substrate on which the silicon single crystal film is formed includes a method of providing a release layer between the substrate and the device as shown in FIG. 10 and removing the release layer by etching. Alternatively, there is a method of removing the entire substrate by an etch-back process as shown in FIG.

【０００５】上記基板下の剥離層を除去する方法では、
先ず、半導体基板１の表面側から剥離層２を介してディ
バイス３を形成する(図１０(a))。そして、ディバイス
３上にＵＶ(紫外線)キュアエポキシ４を塗布し(図１０
(b))、上記ディバイス３の箇所である残し部６とこの残
し部６間で成るエッチング用溝５とを形成する(図１０
(c))。こうして、剥離層２除去用のエッチング溶液導入
用アクセスストリート構造を得る。次に、上記ＵＶキュ
アエポキシ３側から透明基板等で成る支持板７を張り合
わせてチャネルを形成する(図１０(d))。そして、この
チャネルに、矢印(Ａ)で示すようにエッチング溶液を走
らせることによって剥離層２を除去し、半導体基板１か
らディバイス３をリフトオフする。In the method of removing the release layer below the substrate,
First, the device 3 is formed from the front surface side of the semiconductor substrate 1 via the release layer 2 (FIG. 10A). Then, a UV (ultraviolet) cure epoxy 4 is applied on the device 3 (FIG. 10).
(b)), a remaining portion 6, which is the location of the device 3, and an etching groove 5 formed between the remaining portions 6 are formed (FIG. 10).
(c)). Thus, an access street structure for introducing an etching solution for removing the release layer 2 is obtained. Next, a channel is formed by bonding a support plate 7 made of a transparent substrate or the like from the UV cure epoxy 3 side (FIG. 10D). Then, the release layer 2 is removed by running an etching solution through the channel as shown by the arrow (A), and the device 3 is lifted off from the semiconductor substrate 1.

【０００６】また、上記基板全体をエッチ除去する方法
では、図１１(a)に示すように、ディバイス１１が形成
されたＳＯＩ構造シリコンウエハ１２を接着剤１３でガ
ラス等の透明絶縁体で成る支持板としての上部基板１４
に接着する。このウエハをＫＯＨ(水酸化カリウム)また
は同等溶液に入れ、酸化物層１５との高い選択比２０
０：１を利用して図１１(b)に示すようにシリコン基板
１６をエッチ除去する。尚、１７は、薄いシリコン単結
晶フィルムである。In the method of etching and removing the entire substrate, as shown in FIG. 11A, an SOI structure silicon wafer 12 on which a device 11 is formed is supported by an adhesive 13 made of a transparent insulator such as glass. Upper substrate 14 as a plate
Glue to The wafer is placed in KOH (potassium hydroxide) or equivalent solution and has a high selectivity with oxide layer 15 of 20.
Using 0: 1, the silicon substrate 16 is etched away as shown in FIG. Reference numeral 17 denotes a thin silicon single crystal film.

【０００７】さらに、上記従来例２には、ＧeＳi(シリ
化ゲルマニュウム)を中間エッチストップ層としたシリ
コン薄膜転写法が開示されている(図１２)。このシリコ
ン薄膜転写法においては、図１２(a)に示すように、Ｇe
Ｓi層２１を介してディバイス（ＴＦＴ)２２が形成され
たシリコンウエハ２３を、図１２(b)に示すように、エ
ポキシ接着剤２４によってガラスまたは他の基板２５に
マウントする。そして、ＫＯＨに浸漬して、先ずシリコ
ンウエハ２３のみに選択エッチを行い、次にＧeＳi層２
１を別途選択エッチする。Further, the above-mentioned prior art 2 discloses a silicon thin film transfer method using GeSi (germanium silicide) as an intermediate etch stop layer (FIG. 12). In this silicon thin film transfer method, as shown in FIG.
The silicon wafer 23 on which the device (TFT) 22 is formed via the Si layer 21 is mounted on a glass or other substrate 25 with an epoxy adhesive 24 as shown in FIG. Then, the wafer is immersed in KOH to perform selective etching only on the silicon wafer 23 first, and then the GeSi layer 2
Select and etch 1 separately.

【０００８】また、上記従来例２には、上述の基板から
支持板への転写と上記支持板からディスプレイパネル基
板への転写との２つの転写方法として、ＵＶ照射によっ
て剥離する性質を有するＵＶ剥離接着剤をテープの両面
に塗布したＵＶ剥離両面テープを上記支持板との接着に
使用する方法が開示されている(図１３)。この転写方法
では、上記支持板からディスプレイパネル基板への転写
の場合には、透明支持板２６にＵＶ剥離両面テープ２７
によってディバイス２８を転写した後にディバイス２８
が形成されていた基板を除去して図１３(a)の状態にす
る。そうした後に、図１３(b)に示すように、別のＵＶ
剥離両面テープ２９にディバイス２８を当接させて透明
支持板２６側からＵＶ照射してＵＶ剥離両面テープ２７
の接着力を低下させて、ディバイス２８をＵＶ剥離両面
テープ２９に転写する。または、図１３(b')に示すよう
に、エポキシ樹脂３０を塗布した基板３１上にディバイ
ス２８を当接させて、透明支持板２６側からＵＶ照射し
つつ転写する。[0008] Further, in the above-mentioned Conventional Example 2, there are two transfer methods of the above-mentioned transfer from the substrate to the support plate and the transfer from the support plate to the display panel substrate. A method is disclosed in which a UV release double-sided tape in which an adhesive is applied to both sides of the tape is used for bonding to the support plate (FIG. 13). In this transfer method, in the case of transfer from the support plate to the display panel substrate, a UV release double-sided tape 27 is attached to the transparent support plate 26.
Device 28 after transferring device 28
The substrate on which is formed is removed to obtain the state shown in FIG. After that, as shown in FIG.
The device 28 is brought into contact with the release double-sided tape 29, and UV is irradiated from the transparent support plate 26 side to the UV release double-sided tape 27.
, The device 28 is transferred to the UV peeling double-sided tape 29. Alternatively, as shown in FIG. 13B ', the device 28 is brought into contact with the substrate 31 on which the epoxy resin 30 is applied, and the transfer is performed while irradiating UV from the transparent support plate 26 side.

【０００９】さらに、上記従来例２には、基板上に密に
形成したディバイスを粗に配置し直す転写方法が開示さ
れている(図１４)。先ず、図１４(a)に示すように、接
着剤付きの伸縮性基板３５にディバイス３６を転写した
後に、図１４(b)に示すように、各ディバイス３６毎に
ディバイス３６の間隔と位置とをモニタしながら、伸縮
性基板３５をＸ方向へ伸張してＸ方向のディバイス３６
の間隔を所定間隔にする。次に、図１４(c)に示すよう
に、伸縮性基板３５をＹ方向へ伸張してＹ方向のディバ
イス３６の間隔を所定間隔にする。そうした後、ディバ
イス３６をディスプレイパネル基板(図示せず)に転写す
る。他の方法として、テープ上のディバイスチップを回
転ドラム上の他のテープ上に転写することによって、機
械的にディバイス間隔を変換させる方法も開示されてい
る。Further, the above-mentioned prior art 2 discloses a transfer method in which devices densely formed on a substrate are roughly arranged (FIG. 14). First, as shown in FIG. 14 (a), after transferring the devices 36 to a stretchable substrate 35 with an adhesive, as shown in FIG. 14 (b), the intervals and positions of the devices 36 for each device 36 are determined. The stretchable substrate 35 is extended in the X direction while monitoring the
At a predetermined interval. Next, as shown in FIG. 14 (c), the stretchable substrate 35 is extended in the Y direction, and the interval between the devices 36 in the Y direction is set to a predetermined interval. After that, the device 36 is transferred to a display panel substrate (not shown). As another method, a method of mechanically changing a device interval by transferring a device chip on a tape onto another tape on a rotating drum is disclosed.

【００１０】[0010]

【発明が解決しようとする課題】しかしながら、上記従
来の表示用トランジスタアレイパネルの形成方法には、
以下のような問題がある。However, the above-mentioned conventional method for forming a transistor array panel for display includes the following.
There are the following problems.

【００１１】すなわち、従来例１では、パネルの高輝度
化,高精細化,広視野角化の点で問題がある。すなわち、
能動素子(ＴＦＴ)および受動素子(画素電極,補助電極,
電極配線等)を同時に形成した複数枚の単結晶シリコン
薄膜を、ガラス基板上に敷き詰めている。ところが、従
来の張り合わせ材料や精度では、ダイシング加工精度や
接着加工精度の点で張り合わせ箇所の余裕代を目的とす
る素子ピッチの半分にできない。そのために、各単結晶
シリコン薄膜のつなぎ目部における透過光量とつなぎ目
以外の箇所における透過光量とが異なることになり、例
えば視野角によって表示むら等が発生する。したがっ
て、パネルの輝度,精細度,視野角を確保するのに技術的
に困難なのである。That is, the conventional example 1 has a problem in that the panel has high brightness, high definition, and wide viewing angle. That is,
Active element (TFT) and passive element (pixel electrode, auxiliary electrode,
A plurality of single-crystal silicon thin films on which electrode wirings and the like are simultaneously formed are spread over a glass substrate. However, with the conventional bonding material and accuracy, the element pitch cannot be reduced to half of the element pitch aiming at the margin of the bonding portion in terms of the dicing processing accuracy and the bonding processing accuracy. For this reason, the amount of transmitted light at the joint portion of each single-crystal silicon thin film differs from the amount of transmitted light at a portion other than the joint, and display unevenness occurs due to, for example, a viewing angle. Therefore, it is technically difficult to ensure the brightness, definition, and viewing angle of the panel.

【００１２】また、従来例１および従来例２に開示され
た単結晶シリコン薄膜に形成されたＴＦＴアレイをパネ
ル用基板に転写する方法は、単結晶シリコン薄膜上のＴ
ＦＴ数とパネル用基板上のＴＦＴ数とが１：１の関係に
在り、パネル用基板に直接ＴＦＴアレイを作り込む方法
に比べて工数が転写プロセス分だけ増加することにな
り、コストがアップするという問題がある。Further, the method of transferring a TFT array formed on a single-crystal silicon thin film to a panel substrate disclosed in Conventional Example 1 and Conventional Example 2 is based on the method of transferring a TFT array on a single-crystal silicon thin film.
Since the number of FTs and the number of TFTs on the panel substrate are in a 1: 1 relationship, the number of steps is increased by the transfer process as compared with the method of directly forming a TFT array on the panel substrate, and the cost is increased. There is a problem.

【００１３】また、従来例２に開示されている基板上に
密に形成したディバイスを粗に配置し直す転写方法は、
伸縮性基板の伸長時の不動点(支点)がディバイスチップ
の接着面のどの位置になるかによって、ディバイス位置
が最小でチップサイズ(≧２０μm)だけずれるという本
質的な問題を抱えている。そのために、ディバイスチッ
プ毎の精密位置制御が不可欠になる。したがって、少な
くとも１μm程度の位置合わせ精度が必要な高精細ＴＦ
Ｔアレイパネルの形成には、ＴＦＴディバイスチップ毎
の位置計測と制御を含む位置合わせに多大な時間を要す
る。さらに、熱膨張係数の大きな樹脂フィルムへの転写
の場合には、位置決め前後の温度/応力変動によって位
置合わせ精度が損なわれ易い。以上の理由から、量産技
術として採用することには極めて大きな問題がある。The transfer method disclosed in Conventional Example 2 for arranging devices densely formed on a substrate in a coarse manner is as follows.
There is an essential problem that the device position is at a minimum and shifted by the chip size (≧ 20 μm) depending on the position of the fixed point (fulcrum) of the stretchable substrate at the time of extension on the bonding surface of the device chip. Therefore, precise position control for each device chip is indispensable. Therefore, a high-definition TF that requires an alignment accuracy of at least about 1 μm
In the formation of the T array panel, a great deal of time is required for alignment including position measurement and control for each TFT device chip. Further, in the case of transfer to a resin film having a large coefficient of thermal expansion, the accuracy of alignment tends to be impaired due to temperature / stress fluctuations before and after positioning. For the above reasons, there is a very large problem in adopting it as a mass production technology.

【００１４】そこで、この発明の目的は、製造コストの
大幅な削減を可能にする表示用トランジスタアレイパネ
ルの形成方法を提供することにある。SUMMARY OF THE INVENTION An object of the present invention is to provide a method for forming a transistor array panel for display which enables a significant reduction in manufacturing cost.

【００１５】[0015]

【課題を解決するための手段】上記目的を達成するた
め、請求項１に係る発明の表示用トランジスタアレイパ
ネルの形成方法は、基板上に,画素の一方向への配列ピ
ッチｄxを２以上の自然数ｍで除したｄx/ｍのピッチ,お
よび,他方向への配列ピッチｄyを２以上の自然数ｎで除
したｄy/ｎのピッチで素子を設ける工程と、上記基板上
に設けられた素子のうち,上記画素の配列ピッチｄx,ｄy
に対応する素子のみを選択的に他の基板に転写する工程
を備えたことを特徴としている。In order to achieve the above object, a method for forming a display transistor array panel according to the first aspect of the present invention is directed to a method for forming a display transistor array panel, comprising: A step of providing elements at a pitch of dx / m divided by a natural number m, and a pitch of dy / n obtained by dividing an array pitch dy in the other direction by a natural number n of 2 or more; Of these, the pixel arrangement pitch dx, dy
Is selectively transferred to another substrate.

【００１６】上記構成によれば、最終的に表示用トラン
ジスタアレイに形成される画素数の(ｍ×ｎ)倍の素子が
基板上に設けられている。したがって、上記素子が設け
られた１枚の基板から(ｍ×ｎ)枚の表示用トランジスタ
アレイパネルを形成することが可能となり、上記素子を
形成する場合のコストが１/(ｍ×ｎ)に低減される。According to the above configuration, the number of elements which is (m × n) times the number of pixels finally formed in the display transistor array is provided on the substrate. Therefore, it becomes possible to form (m × n) display transistor array panels from one substrate provided with the above elements, and the cost of forming the above elements is reduced to 1 / (m × n). Reduced.

【００１７】さらに、上記構成によれば、上記素子が設
けられた１枚の基板から他の基板上への素子の選択転写
を(ｍ×ｎ)回繰り返すことによって、上記素子の一方向
への配列ピッチがｄxであり、他方向への配列ピッチが
ｄyであると共に、上記素子が形成設けられていた基板
の大きさの(ｍ×ｎ)倍の大きさの上記他の基板が得られ
る。こうして、上記素子の形成に要する材料費が低減さ
れる。Further, according to the above configuration, the selective transfer of the element from one substrate provided with the element to another substrate is repeated (m × n) times, so that the element is transferred in one direction. The arrangement pitch is dx, the arrangement pitch in the other direction is dy, and the other substrate having a size (m × n) times the size of the substrate on which the element is formed is provided. Thus, the material cost required for forming the element is reduced.

【００１８】また、請求項２に係る発明の表示用トラン
ジスタアレイパネルの形成方法は、第１の基板上に,画
素の一方向への配列ピッチｄxを２以上の自然数ｍで除
したｄx/ｍのピッチ,および,他方向への配列ピッチｄy
を２以上の自然数ｎで除したｄy/ｎのピッチで素子を形
成する工程と、上記第１の基板上に形成された素子を第
２の基板上に全体転写する工程と、上記第１の基板を除
去して上記素子を上記第２の基板上に孤立配列させる工
程と、記第２の基板上に転写された素子のうち,上記画
素の配列ピッチｄx,ｄyに対応する素子のみを選択的に
表示用トランジスタアレイ用の第３の基板に転写する工
程を備えたことを特徴としている。According to a second aspect of the present invention, there is provided a method for forming a display transistor array panel, comprising the steps of: dx / m, wherein an array pitch dx in one direction of a pixel is divided by a natural number m of 2 or more on a first substrate. Pitch and array pitch dy in the other direction
Forming a device at a pitch of dy / n obtained by dividing by a natural number n of 2 or more; transferring the entire device formed on the first substrate onto a second substrate; Removing the substrate and arranging the elements in isolation on the second substrate; and selecting only the elements corresponding to the pixel arrangement pitches dx and dy from the elements transferred on the second substrate. And a step of transferring to a third substrate for a display transistor array.

【００１９】上記構成によれば、最終的に表示用トラン
ジスタアレイ用の第３の基板上に形成される画素数の
(ｍ×ｎ)倍の素子が、第１の基板上に形成されている。
したがって、上記素子が形成された１枚の第１の基板か
ら(ｍ×ｎ)枚の第３の基板を形成することが可能とな
り、上記第１の基板上への素子形成コストが１/(ｍ×
ｎ)に低減される。According to the above configuration, the number of pixels finally formed on the third substrate for the display transistor array is reduced.
(m × n) times elements are formed on the first substrate.
Therefore, it is possible to form (m × n) third substrates from one first substrate on which the above elements are formed, and the cost of forming elements on the first substrate is 1 / ( mx
n).

【００２０】また、請求項３に係る発明は、請求項１あ
るいは請求項２に係る発明の表示用トランジスタアレイ
パネルの形成方法において、上記素子が選択転写される
基板上の位置には、上記素子が嵌合される凹部が形成さ
れていることを特徴としている。According to a third aspect of the present invention, in the method of forming a display transistor array panel according to the first or second aspect, the element is selectively transferred to a position on the substrate. Is formed in which a concave portion is formed.

【００２１】上記構成によれば、上記素子が選択転写さ
れる基板上の位置には凹部が形成されているので、上記
凹部に接着剤層を形成することによって、上記素子の選
択転写が更に容易に行われる。According to the above configuration, since the concave portion is formed at the position on the substrate where the element is selectively transferred, the selective transfer of the element is further facilitated by forming the adhesive layer in the concave portion. Done in

【００２２】また、請求項４に係る発明は、請求項１あ
るいは請求項２に係る発明の表示用トランジスタアレイ
パネルの形成方法において、上記素子が選択転写される
基板上の位置には、接着剤層が選択的に形成されている
ことを特徴としている。According to a fourth aspect of the present invention, in the method of forming a display transistor array panel according to the first or second aspect of the invention, an adhesive is provided at a position on the substrate where the element is selectively transferred. It is characterized in that the layer is selectively formed.

【００２３】上記構成によれば、上記素子が選択転写さ
れる基板上の位置に接着剤層が選択的に形成されている
ので、上記素子の選択転写が更に容易に行われる。According to the above configuration, since the adhesive layer is selectively formed at the position on the substrate where the element is selectively transferred, the selective transfer of the element is further easily performed.

【００２４】また、請求項５に係る発明は、請求項１あ
るいは請求項２に係る発明の表示用トランジスタアレイ
パネルの形成方法において、上記素子は順スタガ型のＴ
ＦＴであることを特徴としている。According to a fifth aspect of the present invention, in the method of forming a display transistor array panel according to the first or second aspect of the present invention, the element is a forward staggered T type.
It is characterized by being FT.

【００２５】上記構成によれば、基板上への順スタガ型
ＴＦＴの形成コストが１/(ｍ×ｎ)に低減される。According to the above configuration, the formation cost of the forward stagger type TFT on the substrate is reduced to 1 / (m × n).

【００２６】また、請求項６に係る発明は、請求項１あ
るいは請求項２に係る発明の表示用トランジスタアレイ
パネルの形成方法において、上記素子は逆スタガ型のＴ
ＦＴであることを特徴としている。According to a sixth aspect of the present invention, in the method for forming a display transistor array panel according to the first or second aspect, the element is an inverted staggered T-type.
It is characterized by being FT.

【００２７】上記構成によれば、上記基板上への逆スタ
ガ型ＴＦＴの形成コストが１/(ｍ×ｎ)に低減される。According to the above configuration, the cost of forming the inverted staggered TFT on the substrate is reduced to 1 / (m × n).

【００２８】また、請求項７に係る発明は、請求項１あ
るいは請求項２に係る発明の表示用トランジスタアレイ
パネルの形成方法において、上記素子はコプレーナ型の
ＴＦＴであることを特徴としている。According to a seventh aspect of the present invention, in the method of forming a display transistor array panel according to the first or second aspect, the element is a coplanar TFT.

【００２９】上記構成によれば、上記基板上へのコプレ
ーナ型ＴＦＴの形成コストが１/(ｍ×ｎ)に低減され
る。According to the above configuration, the cost of forming a coplanar TFT on the substrate is reduced to 1 / (mxn).

【００３０】また、請求項８に係る発明は、請求項５乃
至請求項７の何れか一つに係る発明の表示用トランジス
タアレイパネルの形成方法において、上記素子は配線交
差部をも含んでいることを特徴としている。According to an eighth aspect of the present invention, in the method of forming a display transistor array panel according to any one of the fifth to seventh aspects, the element includes a wiring intersection. It is characterized by:

【００３１】上記構成によれば、上記基板上への配線交
差部をも含むＴＦＴの形成コストが１/（ｍ×ｎ）に低
減される。According to the above configuration, the cost of forming the TFT including the wiring intersection on the substrate is reduced to 1 / (m × n).

【００３２】また、請求項９に係る発明は、請求項２に
係る発明の表示用トランジスタアレイパネルの形成方法
において、上記第１の基板はシリコン基板であることを
特徴としている。According to a ninth aspect of the present invention, in the method for forming a display transistor array panel according to the second aspect of the present invention, the first substrate is a silicon substrate.

【００３３】上記構成によれば、上記第１の基板はシリ
コン基板であるから上記素子を高密度に形成できる。し
たがって、上記自然数ｍ,ｎを容易に大きくすることが
可能となり、上記第１の基板上への素子形成コストが大
幅に低減される。According to the above configuration, since the first substrate is a silicon substrate, the elements can be formed at a high density. Therefore, the natural numbers m and n can be easily increased, and the cost of forming an element on the first substrate is greatly reduced.

【００３４】また、請求項１０に係る発明は、請求項２
に係る発明の表示用トランジスタアレイパネルの形成方
法において、上記第１の基板はガラス基板であることを
特徴としている。The invention according to claim 10 is the second invention.
In the method for forming a display transistor array panel according to the invention, the first substrate is a glass substrate.

【００３５】上記構成によれば、上記第１の基板はガラ
ス基板であるから、大型の第１の基板の形成が可能とな
り、大型の表示用トランジスタアレイパネルが容易に形
成される。According to the above configuration, since the first substrate is a glass substrate, a large-sized first substrate can be formed, and a large-sized display transistor array panel can be easily formed.

【００３６】また、請求項１１に係る発明は、請求項２
に係る発明の表示用トランジスタアレイパネルの形成方
法において、上記第１の基板上の素子の上記第２の基板
上への全体転写は,光によって接着力が低下する接着剤
によって行い、上記第２の基板上の素子の上記第３の基
板上への選択転写は,上記第２の基板の裏面から上記画
素の配列ピッチｄx,ｄyに対応する素子の箇所への光照
射によって転写の対象となる素子のみを選択的に上記第
２の基板から剥離することによって行うことを特徴とし
ている。The invention according to claim 11 is based on claim 2
In the method for forming a display transistor array panel according to the invention, the entire transfer of the elements on the first substrate onto the second substrate is performed by an adhesive whose adhesive force is reduced by light, and The selective transfer of the elements on the third substrate onto the third substrate is a transfer target by irradiating light from the back surface of the second substrate to the element locations corresponding to the pixel arrangement pitches dx and dy. It is characterized in that the process is performed by selectively peeling only the element from the second substrate.

【００３７】上記構成によれば、光によって接着力が低
下する接着剤の塗布および上記第２の基板の裏面からの
光の選択照射という簡単な方法によって、上記第２の基
板上の素子の上記第３の基板上への選択転写が行われ
る。According to the above configuration, the element on the second substrate can be formed by a simple method of applying an adhesive whose adhesive strength is reduced by light and selectively irradiating light from the back surface of the second substrate. Selective transfer onto the third substrate is performed.

【００３８】また、請求項１２に係る発明は、請求項２
に係る発明の表示用トランジスタアレイパネルの形成方
法において、上記第１の基板上にフッ化水素酸に対して
耐性を有する透明絶縁膜を形成し、この透明絶縁膜上に
上記素子を形成することを特徴としている。The twelfth aspect of the present invention is the second aspect of the present invention.
In the method for forming a display transistor array panel according to the invention, a transparent insulating film having resistance to hydrofluoric acid is formed on the first substrate, and the element is formed on the transparent insulating film. It is characterized by.

【００３９】上記構成によれば、上記第１の基板の除去
に際して、エッチャントとしてフッ化水素酸が使用され
た場合に、フッ化水素酸に対して耐性を有する透明絶縁
膜の存在によって上記素子が保護される。According to the above configuration, when the first substrate is removed, when the hydrofluoric acid is used as an etchant, the element is removed due to the presence of the transparent insulating film having resistance to hydrofluoric acid. Protected.

【００４０】また、請求項１３に係る発明は、請求項１
２に係る発明の表示用トランジスタアレイパネルの形成
方法において、上記フッ化水素酸に対して耐性を有する
透明絶縁膜は、酸化タンタル膜あるいはダイヤモンド膜
の何れ一方であることを特徴としている。The invention according to claim 13 is based on claim 1
In the method for forming a display transistor array panel according to the second aspect, the transparent insulating film having resistance to hydrofluoric acid is one of a tantalum oxide film and a diamond film.

【００４１】上記構成によれば、上記第１の基板除去用
のエッチャントとしてフッ化水素酸が使用された場合
に、酸化タンタル膜あるいはダイヤモンド膜の何れ一方
の存在によって上記素子が確実に保護される。According to the above configuration, when hydrofluoric acid is used as the etchant for removing the first substrate, the element is reliably protected by the presence of either the tantalum oxide film or the diamond film. .

【００４２】[0042]

【発明の実施の形態】以下、この発明を図示の実施の形
態により詳細に説明する。DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, the present invention will be described in detail with reference to the illustrated embodiments.

【００４３】＜第１実施の形態＞図１および図２は、本
実施の形態の表示用トランジスタアレイパネルの形成方
法における手順を示す図である。本実施の形態において
は、第１の基板としてシリコン(Ｓi)基板を用いてい
る。<First Embodiment> FIGS. 1 and 2 are views showing a procedure in a method of forming a display transistor array panel according to the present embodiment. In the present embodiment, a silicon (Si) substrate is used as the first substrate.

【００４４】図１(a)に示すように、上記第１の基板と
してのＳi基板４１上に透明絶縁膜としてＳi酸化膜４２
を形成した後、ｉ線スパッタを用いたフォトプロセスを
含む公知の素子形成プロセスを行って、ＴＦＴ素子４３
を素子分離溝４４を隔てて所定のピッチで形成する。こ
こで、上記ピッチは、目的とする表示用トランジスタア
レイパネルの画素ドットの配列ピッチｄx,ｄyを、「２」
以上の自然数ｍ,ｎで除した値ｄx/ｍ,ｄy/ｎである。ま
た、形成するＴＦＴ素子４３は、例えばＴＦＴと周辺電
極配線の一部を含むものであるが、画素電極は含まな
い。尚、形成するＴＦＴの構造については後に詳述す
る。As shown in FIG. 1A, a Si oxide film 42 as a transparent insulating film is formed on a Si substrate 41 as the first substrate.
After the formation of the TFT element 43, a well-known element formation process including a photo process using i-line sputtering is performed to form the TFT element 43.
Are formed at a predetermined pitch with the element isolation groove 44 therebetween. Here, the pitch is determined by setting the pixel dot arrangement pitch dx, dy of the target display transistor array panel to “2”.
The values dx / m and dy / n divided by the natural numbers m and n described above. The TFT element 43 to be formed includes, for example, a TFT and a part of the peripheral electrode wiring, but does not include a pixel electrode. The structure of the TFT to be formed will be described later in detail.

【００４５】次に、図１(b)に示すように、上記ＴＦＴ
素子４３側にＵＶ剥離樹脂４６を塗布し、第２の基板で
ある光透過性基板としてのガラス基板４５を張り付け
る。ここで、ＵＶ剥離樹脂４６としては、シリコン(メ
タ)アクリレート添加のアクリル系樹脂や紫外線照射で
接着力が低下するＵＶ硬化型粘着剤等を用いる。次に、
図１(c)に示すように、Ｓi基板(第１の基板)４１をＫＯ
Ｈでエッチング除去した後に、ＴＦＴ素子分離溝４４の
箇所のＳi酸化膜４２に対してＴＦＴ素子分離エッチン
グを行って個々のＴＦＴ素子４３を孤立した状態にす
る。Next, as shown in FIG.
A UV release resin 46 is applied to the element 43 side, and a glass substrate 45 as a light-transmitting substrate, which is a second substrate, is attached. Here, as the UV release resin 46, an acrylic resin to which silicon (meth) acrylate is added, a UV curable adhesive whose adhesive strength is reduced by irradiation with ultraviolet rays, or the like is used. next,
As shown in FIG. 1C, the Si substrate (first substrate) 41 is KO
After the etching removal with H, the TFT element isolation etching is performed on the Si oxide film 42 at the location of the TFT element isolation groove 44, so that the individual TFT elements 43 are isolated.

【００４６】次に、図１(d)に示すように、ＴＦＴパネ
ル用の第３の基板であるガラス基板４７に接着樹脂４８
を塗布したものを、アライメントを行いつつガラス基板
(第２の基板)４５に近接させる。そして、フォトマスク
４９を用いて、接着樹脂４８における転写の対象となる
(後に画素を構成する)ＴＦＴ素子４３の箇所に位置する
部分を紫外線５０を照射して半硬化させて接着性を高
め、その半硬化部分５１を転写対象のＴＦＴ素子４３に
押し付けてガラス基板(第３の基板)４７を貼り合わせ
る。尚、接着樹脂４８としては、例えばアクリレート系
のＵＶ硬化樹脂やＵＶ硬化エポキシ系樹脂等を用いる。Next, as shown in FIG. 1D, an adhesive resin 48 is attached to a glass substrate 47 which is a third substrate for the TFT panel.
The glass substrate is coated with
(The second substrate) 45. Then, the photomask 49 is used as a transfer target on the adhesive resin 48.
A portion located at the position of the TFT element 43 (which constitutes a pixel later) is irradiated with ultraviolet rays 50 to be semi-cured to increase the adhesiveness, and the semi-cured part 51 is pressed against the TFT element 43 to be transferred to a glass substrate ( A third substrate 47 is attached. In addition, as the adhesive resin 48, for example, an acrylate UV curable resin, a UV curable epoxy resin, or the like is used.

【００４７】また、上記第３の基板を貼り合わせる方法
として、図２(d')に示す方法を用いても差し支えない。
すなわち、第３の基板５５における転写対象のＴＦＴ素
子４３の箇所に位置する部分を、例えばＣＦ4やＣＨＦ3
を用いたドライエッチ(ＲＩＥ)によって、ＴＦＴ素子４
３のチップが入るサイズの凹部５６を形成し、この凹部
５６のみに予め接着樹脂５７を塗布しておく。そして、
凹部５６に転写対象のＴＦＴ素子４３を嵌合して第３の
基板５５を貼り合わせるのである。As a method for bonding the third substrate, a method shown in FIG. 2D 'may be used.
That is, the portion of the third substrate 55 located at the position of the TFT element 43 to be transferred is, for example, CF 4 or CHF 3
TFT device 4 by dry etching (RIE) using
A recess 56 having a size to accommodate the chip No. 3 is formed, and an adhesive resin 57 is applied to only the recess 56 in advance. And
The TFT substrate 43 to be transferred is fitted into the concave portion 56, and the third substrate 55 is bonded.

【００４８】次に、図２(e)に示すように、フォトマス
ク６１を用いて、ガラス基板４５(第２の基板：光透過
性基板)側から、ＵＶ剥離樹脂４６における転写対象の
ＴＦＴ素子４３の箇所の部分に紫外線６２を選択的に照
射して、ＵＶ剥離樹脂４６の接着力を低下させてＴＦＴ
素子４３との密着性を低減させる。Next, as shown in FIG. 2E, using a photomask 61, a TFT element to be transferred on a UV release resin 46 from a glass substrate 45 (second substrate: light transmitting substrate) side. 43 is selectively irradiated with ultraviolet rays 62 to reduce the adhesive force of the UV release resin 46 to reduce
The adhesion with the element 43 is reduced.

【００４９】以上の処理によって、上記転写対象のＴＦ
Ｔ素子４３は隣接しているＴＦＴ素子４３とは孤立して
おり、ガラス基板(第２の基板)４５との間のＵＶ剥離樹
脂４６は接着力が低下している。したがって、図２(f)
に示すように、パネル用のガラス基板(第３の基板)４７
に転写対象のＴＦＴ素子４３のみが移し取られる(転写
接着)される。そして、未露光のＴＦＴ素子４３は、ガ
ラス基板(第３の基板)４７に転写接着されない。尚、未
露光の接着樹脂４８は選択転写後に除去しておく。By the above processing, the TF to be transferred is
The T element 43 is isolated from the adjacent TFT element 43, and the UV peeling resin 46 between the T element 43 and the glass substrate (second substrate) 45 has reduced adhesive strength. Therefore, FIG.
As shown in the figure, a glass substrate (third substrate) 47 for the panel
Then, only the TFT element 43 to be transferred is transferred (transfer bonding). The unexposed TFT elements 43 are not transferred and bonded to the glass substrate (third substrate) 47. The unexposed adhesive resin 48 is removed after the selective transfer.

【００５０】最後に、受動素子部形成プロセスを行う。
この受動素子部形成プロセスでは、図３に示すように、
上記パネル用のガラス基板(第３の基板)４７上に画素ド
ットの配列ピッチｄx,ｄyで転写接着されたＴＦＴ素子
４３に、データ信号線６５に接続するためのソース電極
配線６６,走査信号線６７に接続するためのゲート電極
配線６８およびドレイン電極配線６９を配線する。さら
に、ドレイン電極配線６９に接続される液晶駆動用の画
素電極７０を形成する。その場合の配線間絶縁膜とし
て、例えばポリイミド膜を用いる。そして、上述の図１
(c)におけるＴＦＴ素子分離エッチング等の際にＴＦＴ
素子４３を保護するためにＴＦＴ素子４３を覆って形成
されている例えばＳi酸化膜(図示せず)に、電極接続用
のコンタクトホールを穴あけエッチングで形成する。そ
して、ガラス基板(第３の基板)４７上のデータ信号線６
５や走査信号線６７とＴＦＴ素子４３の電極との接続等
を行う。Finally, a passive element portion forming process is performed.
In this passive element portion forming process, as shown in FIG.
The source electrode wiring 66 for connecting to the data signal line 65, the scanning signal line, and the TFT element 43 transferred and adhered at the pixel dot arrangement pitch dx, dy on the glass substrate (third substrate) 47 for the panel. A gate electrode wiring 68 and a drain electrode wiring 69 for connecting to the gate 67 are provided. Further, a pixel electrode 70 for driving liquid crystal connected to the drain electrode wiring 69 is formed. In this case, for example, a polyimide film is used as the inter-wiring insulating film. Then, FIG.
In the case of TFT element separation etching in (c), the TFT
In order to protect the element 43, a contact hole for electrode connection is formed by, for example, drilling and etching in a Si oxide film (not shown) formed so as to cover the TFT element 43. The data signal lines 6 on the glass substrate (third substrate) 47
5 and the scanning signal lines 67 and the electrodes of the TFT elements 43 are connected.

【００５１】こうして、図４に示すような表示用トラン
ジスタアレイパネルが形成される。尚、７１はカラーフ
ィルタガラス基板であり、７２はＲＧＢのカラーフィル
タである。また、上記配線６５〜６９および画素電極７
０は、ＴＦＴ素子４３が転写接着される前に、予めガラ
ス基板(第３の基板)４７上に形成しておいても構わな
い。Thus, a display transistor array panel as shown in FIG. 4 is formed. In addition, 71 is a color filter glass substrate, and 72 is an RGB color filter. The wirings 65 to 69 and the pixel electrode 7
0 may be formed on a glass substrate (third substrate) 47 in advance before the TFT element 43 is transferred and bonded.

【００５２】従来より、表示用トランジスタアレイパネ
ルに採用されているＴＦＴ素子の構造として、順スタガ
構造,逆スタガ構造およびコプレーナ構造の３種類があ
る。図５は順スタガＴＦＴの構造の一例を示し、図５
(a)は断面図であり、図５(b)は平面図である。順スタガ
ＴＦＴでは、ゲート電極８１が、ソース電極８２下のオ
ーミック・コンタクト層８３とドレイン電極８４下のオ
ーミック・コンタクト層８５とに接続するチャネル層８
６の上側に、ゲート絶縁膜８７を介して形成されてい
る。尚、８９は、上記選択転写後の配線プロセスにおい
てＳi酸化膜８８に形成されるゲート電極７１に対する
コンタクトホールである。同様に、９０はソース電極８
２に対するコンタクトホールであり、９１はドレイン電
極８４に対するコンタクトホールである。Conventionally, there are three types of structures of TFT elements employed in a transistor array panel for display, a forward stagger structure, an inverse stagger structure, and a coplanar structure. FIG. 5 shows an example of the structure of the forward staggered TFT.
5A is a sectional view, and FIG. 5B is a plan view. In the forward stagger TFT, the gate electrode 81 is connected to the ohmic contact layer 83 below the source electrode 82 and the ohmic contact layer 85 below the drain electrode 84 by the channel layer 8 connected to the ohmic contact layer 85.
On the upper side of 6, a gate insulating film 87 is formed. Reference numeral 89 denotes a contact hole for the gate electrode 71 formed in the Si oxide film 88 in the wiring process after the selective transfer. Similarly, 90 is the source electrode 8
Reference numeral 91 denotes a contact hole for the drain electrode 84.

【００５３】また、図６は、上記逆スタガＴＦＴの構造
の一例の断面図を示す。逆スタガＴＦＴでは、ゲート電
極１０１が、ソース電極１０２とドレイン電極１０３と
に接続するチャネル層１０４の下側に、ゲート絶縁膜１
０５及び金属酸化膜１０６を介して形成されている。
尚、１０７,１０８はオーミック・コンタクト層であり、
１１０はＳi酸化膜１０９に形成されたソース電極１０
２に対するコンタクトホールであり、１１１はドレイン
電極１０３に対するコンタクトホールである。FIG. 6 is a sectional view showing an example of the structure of the inverted staggered TFT. In the inverted staggered TFT, the gate electrode 101 has a gate insulating film 1 under the channel layer 104 connected to the source electrode 102 and the drain electrode 103.
05 and the metal oxide film 106.
Incidentally, 107 and 108 are ohmic contact layers,
Reference numeral 110 denotes the source electrode 10 formed on the Si oxide film 109.
Reference numeral 111 denotes a contact hole for the drain electrode 103.

【００５４】また、図７は、上記コプレーナＴＦＴの構
造の断面図を示す。コプレーナＴＦＴでは、ゲート電極
１２１が、ソース電極１２２とドレイン電極１２３とを
接続するオーミック・コンタクト層１２４の中間部に形
成されるチャネル層１２５の上側に、ゲート絶縁膜１２
６を介して形成されている。尚、１２８はＳi酸化膜１
２７に形成されたソース電極１２２に対するコンタクト
ホールであり、１２９はドレイン電極１２３に対するコ
ンタクトホールである。FIG. 7 is a sectional view showing the structure of the coplanar TFT. In the coplanar TFT, the gate electrode 121 is formed on the gate insulating film 12 above the channel layer 125 formed in the middle of the ohmic contact layer 124 connecting the source electrode 122 and the drain electrode 123.
6 are formed. Incidentally, 128 is the Si oxide film 1
Reference numeral 129 denotes a contact hole for the source electrode 122, and reference numeral 129 denotes a contact hole for the drain electrode 123.

【００５５】上記順スタガＴＦＴ,逆スタガＴＦＴおよ
びコプレーナＴＦＴの何れの場合にも、ガラス基板(第
２の基板)４５への全体転写後におけるＮaＯＨ(水酸化
ナトリウム)あるいはＫＯＨをエッチャントとしたＳi基
板(第１の基板)４１への選択エッチングを行う際に、上
記エッチャントに耐性のあるＳi酸化膜４２でＴＦＴが
保護される構成になっている。したがって、何れの構成
の場合も、本実施の形態の表示用トランジスタアレイパ
ネルの形成方法が適用可能である。尚、上記保護膜４２
は、Ｓi酸化膜に限定されるものではなく、第１の基板
に対する選択エッチング時に使用されるエッチャントに
対して耐性を有する膜であればよい。例えば、第１の基
板がガラス基板である場合には、エッチャントとしての
フッ化水素酸に対して耐性を有する酸化タンタル膜ある
いはダイアモンド膜を上記保護膜として上記ガラス基板
とＴＦＴとの間に形成すればよい。尚、上記保護膜は、
上記第１の基板とＴＦＴとの間のみならず、図５〜図７
に示すように、ＴＦＴの表面および側面にも形成するこ
とが望ましい。In any of the forward stagger TFT, reverse stagger TFT and coplanar TFT, the Si substrate using NaOH (sodium hydroxide) or KOH as an etchant after the entire transfer to the glass substrate (second substrate) 45 is used. When performing selective etching on the (first substrate) 41, the TFT is protected by the Si oxide film 42 resistant to the etchant. Therefore, in any case, the method for forming the display transistor array panel of this embodiment can be applied. The protective film 42
Is not limited to a Si oxide film, but may be any film having resistance to an etchant used at the time of selective etching of the first substrate. For example, when the first substrate is a glass substrate, a tantalum oxide film or a diamond film having resistance to hydrofluoric acid as an etchant is formed between the glass substrate and the TFT as the protective film. I just need. In addition, the said protective film is
5 to 7 as well as between the first substrate and the TFT.
As shown in (1), it is desirable to form it also on the surface and side surface of the TFT.

【００５６】尚、図８は、図６に示す逆スタガＴＦＴに
おけるソース電極１０２に接続されたソース電極配線１
１５とゲート電極配線１１６との交差部１１５の断面図
である。このようなソース電極配線１１５とゲート電極
配線１１６との交差部１１５も、ＴＦＴ素子４３に含め
て、第３の基板４７上に選択転写することが可能であ
る。FIG. 8 shows the source electrode wiring 1 connected to the source electrode 102 in the inverted staggered TFT shown in FIG.
15 is a cross-sectional view of an intersecting portion 115 between a gate electrode 15 and a gate electrode wiring 116. FIG. Such an intersection 115 between the source electrode wiring 115 and the gate electrode wiring 116 can also be included in the TFT element 43 and selectively transferred onto the third substrate 47.

【００５７】上述のように、本実施の形態においては、
Ｓi基板で成る第１の基板４１上にＴＦＴ素子４３を素
子分離溝４４を隔ててピッチｄx/ｍ,ｄy/ｎで形成す
る。ここで、ｄx,ｄyは画素ドットの配列ピッチであ
り、ｍ,ｎは「２」以上の自然数である。そして、ＴＦＴ
素子４３側にＵＶ剥離樹脂４６で第２の基板４５を張り
付けた後、第１の基板４１をエッチング除去し、ＴＦＴ
素子分離エッチングを行って各ＴＦＴ素子４３を分離さ
せる。そして、第３の基板４７に接着樹脂４８で転写対
象のＴＦＴ素子４３のみを選択的に接着させ、第２の基
板４５側から転写対象のＴＦＴ素子４３の箇所に紫外線
６２を選択的に照射してＵＶ剥離樹脂４６の接着力を低
下させて、転写対象の(つまり、画素を構成する)ＴＦＴ
素子４３のみを第３の基板４７に選択転写するのであ
る。As described above, in the present embodiment,
A TFT element 43 is formed on a first substrate 41 made of a Si substrate at a pitch dx / m, dy / n with an element isolation groove 44 therebetween. Here, dx and dy are arrangement pitches of the pixel dots, and m and n are natural numbers of "2" or more. And TFT
After attaching a second substrate 45 to the element 43 with a UV release resin 46, the first substrate 41 is removed by etching,
Each TFT element 43 is separated by performing element separation etching. Then, only the transfer target TFT elements 43 are selectively adhered to the third substrate 47 with the adhesive resin 48, and ultraviolet rays 62 are selectively irradiated from the second substrate 45 to the transfer target TFT elements 43. To reduce the adhesive strength of the UV release resin 46, and to transfer the TFT (that is, constitute a pixel).
Only the element 43 is selectively transferred to the third substrate 47.

【００５８】したがって、上記第２の基板４５上のＴＦ
Ｔ素子４３のピッチｄx/ｍ,ｄy/ｎの第３の基板４７上
でのピッチｄx,ｄyへの拡大を、従来例２の如く伸縮性
基板を用いる転写方法に比して正確に行うことができ
る。したがって、１枚の第２の基板４５を用いて、この
第２の基板４５から第３の基板(パネル用基板)４７への
選択転写を、第２の基板４５をｘ方向へｄx/ｍあるいは
ｙ方向へｄy/ｎだけ移動させながら(ｍ×ｎ)枚の第３の
基板４７に対して行うことによって、第１の基板４１を
１枚作成すれば、(ｍ×ｎ)枚のパネル用基板４７に対し
て同一の選択転写を行うことができる。すなわち、本実
施の形態によれば、第１の基板４１上にＴＦＴ素子４３
を形成するコストを概略１/(ｍ×ｎ)にできる。Therefore, the TF on the second substrate 45
Enlarging the pitch dx / m, dy / n of the T element 43 to the pitch dx, dy on the third substrate 47 more accurately than the transfer method using a stretchable substrate as in Conventional Example 2. Can be. Therefore, using one sheet of the second substrate 45, the selective transfer from the second substrate 45 to the third substrate (panel substrate) 47 is performed by moving the second substrate 45 in the x direction by dx / m or By performing the process on the (m × n) third substrates 47 while moving it by dy / n in the y direction, if one first substrate 41 is formed, (m × n) panels The same selective transfer can be performed on the substrate 47. That is, according to the present embodiment, the TFT element 43 is provided on the first substrate 41.
Can be reduced to approximately 1 / (mxn).

【００５９】このように、本実施の形態によれば、表示
用トランジスタアレイパネルとして必要な画素数のｍ,
ｎ倍のＴＦＴ素子を第１の基板４１上に形成することが
可能となる。したがって、必要画素数と第１の基板上の
ＴＦＴ素子数とが同数の従来の表示用トランジスタアレ
イパネルの形成方法に比して、第１の基板４１に形成す
るＴＦＴ素子密度を１０倍〜１００倍にできる。したが
って、表示用トランジスタアレイパネル製造設備におけ
るイニシャルコストの約３０％を占める成膜工程設備お
よび約２６％を占めるフォト工程設備のスループット
を、実質的に１０倍〜１００倍程度向上させることがで
きる。また、ＴＦＴ素子４３の形成に要する材料費も１
/１０〜１/１００に低減できる。結果として、表示用ト
ランジスタアレイパネルの製造コストの大幅な削減が可
能となるのである。As described above, according to the present embodiment, the number m of pixels required for the display transistor array panel is m,
It becomes possible to form n times as many TFT elements on the first substrate 41. Therefore, the density of the TFT elements formed on the first substrate 41 is increased by a factor of 10 to 100 as compared with the conventional method of forming a transistor array panel for display in which the number of necessary pixels and the number of TFT elements on the first substrate are the same. Can be doubled. Therefore, the throughput of the film forming process equipment occupying about 30% of the initial cost and the photo processing equipment occupying about 26% of the initial cost in the display transistor array panel manufacturing equipment can be substantially improved about 10 to 100 times. Also, the material cost required for forming the TFT element 43 is one.
/ 10 to 1/100. As a result, the manufacturing cost of the display transistor array panel can be significantly reduced.

【００６０】ところで、上記第１の基板４１としてＳi
基板を用いた場合には、基板サイズに制限があるものの
ＴＦＴ素子を高密度に形成できる。そこで、以下のよう
にして、上記基板サイズの制限を超えたサイズの第３の
基板４７を形成することができる。すなわち、ＴＦＴ素
子４３が高密度で形成されたＳi基板(第１の基板)４１
を複数枚形成する。そして、この複数枚のＳi基板(第１
の基板)４１の位置をずらして第２の基板４５に全体転
写することによって、ＴＦＴ素子４３が高密度で転写さ
れた(つまり、自然数ｍ,ｎが大きい)第２の基板４５を
形成するのである。The first substrate 41 is Si
When a substrate is used, TFT elements can be formed at a high density although the size of the substrate is limited. Therefore, a third substrate 47 having a size exceeding the above-described substrate size limit can be formed as follows. That is, the Si substrate (first substrate) 41 on which the TFT elements 43 are formed at a high density.
Are formed. Then, the plurality of Si substrates (first
By shifting the position of the (substrate) 41 and transferring the whole to the second substrate 45, the second substrate 45 on which the TFT elements 43 are transferred at a high density (that is, the natural numbers m and n are large) is formed. is there.

【００６１】上記ガラス基板(第２の基板)４５に、複数
枚のＳi基板(第１の基板)４１上のＴＦＴ素子４３を転
写する場合には、図１(a)〜図１(c)に示す第１の基板４
１から第２の基板４５への転写プロセスに従って、１枚
の第１の基板４１毎にアライメントしつつ第１の基板４
１の枚数だけ転写を繰り返して行えばよい。こうするこ
とによって、複数枚の第１の基板４１上のＴＦＴ素子４
３を１０μm以下の間隔で第２の基板４５上に転写する
ことが可能となる。従来例１の如く、複数枚の第１の基
板を第２の基板上に敷き詰める方法の場合には、第１の
基板形成時のダイシング加工精度や第２の基板への接着
加工精度の点で、各素子を１０μm以下の間隔で配列す
ることは一般には困難である。ところが、本実施の形態
の場合には、第１の基板４１の枚数だけ第２の基板４５
への転写を繰り返せば、ＴＦＴ素子４３を１０μm以下
の間隔で第２の基板４５上に配列することは簡単にでき
るのである。When the TFT elements 43 on a plurality of Si substrates (first substrates) 41 are transferred to the glass substrate (second substrate) 45, FIGS. 1 (a) to 1 (c) First substrate 4 shown in FIG.
In accordance with the transfer process from the first substrate 4 to the second substrate 45, the first substrate 4
The transfer may be repeated by the number of sheets of one. By doing so, the TFT elements 4 on the plurality of first substrates 41 are formed.
3 can be transferred onto the second substrate 45 at an interval of 10 μm or less. In the case of a method in which a plurality of first substrates are spread over a second substrate as in Conventional Example 1, the accuracy of dicing at the time of forming the first substrate and the accuracy of bonding to the second substrate are reduced. It is generally difficult to arrange each element at an interval of 10 μm or less. However, in the case of the present embodiment, the number of the second substrates 45 is equal to the number of the first substrates 41.
By repeating the transfer to the second substrate 45, the TFT elements 43 can be easily arranged on the second substrate 45 at intervals of 10 μm or less.

【００６２】上述の場合、上記第１の基板４１から第２
の基板４５への全体転写の回数が増加する。しかしなが
ら、ＴＦＴ素子４３は高密度に形成されているために自
然数ｍ,ｎの値は大きく、１枚の第２の基板４５から多
数の第３の基板４７を形成できる。したがって、上記全
体転写によるコストアップを埋めて、尚且つコストダウ
ンを図ることができるのである。In the above case, the first substrate 41
The number of times of the entire transfer to the substrate 45 is increased. However, since the TFT elements 43 are formed at a high density, the values of the natural numbers m and n are large, and a large number of third substrates 47 can be formed from one second substrate 45. Therefore, it is possible to compensate for the cost increase due to the whole transfer and to reduce the cost.

【００６３】尚、上記実施の形態においては、紫外線に
対するＵＶ剥離樹脂の性質を利用して選択転写を行って
いる。しかしながら、この発明はこれに限定されるもの
ではなく、例えば、転写側の基板の一方側,他方側ある
いは両側からの静電引力や電磁力を利用して選択転写を
行っても差し支えない。In the above embodiment, the selective transfer is performed by utilizing the properties of the UV release resin against ultraviolet rays. However, the present invention is not limited to this. For example, selective transfer may be performed by using electrostatic attraction or electromagnetic force from one side, the other side, or both sides of the transfer side substrate.

【００６４】＜第２実施の形態＞図９は、本実施の形態
の表示用トランジスタアレイパネルの形成方法における
手順を示す図である。本実施の形態においては、第１の
基板としてガラス基板を用いている。<Second Embodiment> FIG. 9 is a diagram showing a procedure in a method of forming a display transistor array panel according to the present embodiment. In this embodiment mode, a glass substrate is used as the first substrate.

【００６５】図９(a)に示すように、上記第１の基板と
してのガラス基板１３１上に、例えばＳi膜１３２とＳi
窒化膜(あるいはＳi酸化膜)１３３との２層構造で成る
犠牲層１３４を形成する。そうした後、ｉ線スパッタを
用いたフォトプロセスを含む公知の素子形成プロセスを
行って、ＴＦＴ素子１３５を素子分離溝１３６を隔てて
所定のピッチで形成する。ここで、上記ピッチは、目的
とする表示用トランジスタアレイパネルの画素ドットの
配列ピッチｄx,ｄyを、「２」以上の自然数ｍ,ｎで除した
値ｄx/ｍ,ｄy/ｎである。また、形成するＴＦＴ素子１
３５は、例えばＴＦＴと周辺電極配線の一部を含むもの
であるが、画素電極は含まない。尚、形成するＴＦＴの
構造は、上述の順スタガＴＦＴ,逆スタガＴＦＴおよび
コプレーナＴＦＴの何れかである。As shown in FIG. 9A, for example, a Si film 132 and a Si film 132 are formed on a glass substrate 131 as the first substrate.
A sacrificial layer 134 having a two-layer structure with a nitride film (or Si oxide film) 133 is formed. After that, a well-known element forming process including a photo process using i-line sputtering is performed to form the TFT elements 135 at a predetermined pitch with the element separating grooves 136 therebetween. Here, the pitch is a value dx / m, dy / n obtained by dividing the array pitch dx, dy of the pixel dots of the target display transistor array panel by a natural number m, n of "2" or more. Also, the TFT element 1 to be formed
35 includes, for example, a TFT and a part of the peripheral electrode wiring, but does not include a pixel electrode. The structure of the TFT to be formed is any of the above-mentioned forward stagger TFT, reverse stagger TFT, and coplanar TFT.

【００６６】次に、図９(b)に示すように、上記ＴＦＴ
素子１３５側にＵＶ剥離樹脂１３７を塗布し、第２の基
板である光透過性基板としてのガラス基板１３８を張り
付ける。次に、図９(c)に示すように、例えばバッファ
フッ酸等のＳiとの選択比が大きな選択エッチング液１
３９を、真空吸入法によってＴＦＴ素子分離溝１３６に
均一に充填する。こうして、犠牲層１３４におけるＳi
窒化膜(あるいはＳi酸化膜)１３３のみを選択エッチン
グして除去する。Next, as shown in FIG.
A UV release resin 137 is applied to the element 135 side, and a glass substrate 138 as a light-transmitting substrate, which is a second substrate, is attached. Next, as shown in FIG. 9C, a selective etching solution 1 having a high selectivity with respect to Si such as buffered hydrofluoric acid is used.
39 is uniformly filled in the TFT element isolation groove 136 by a vacuum suction method. Thus, the Si in the sacrificial layer 134
Only the nitride film (or Si oxide film) 133 is selectively etched and removed.

【００６７】次に、図９(d)に示すように、上記ガラス
基板(第１の基板)１３１を取り外して、各ＴＦＴ素子１
３５をガラス基板(第２の基板)１３８上に孤立した状態
にする。Next, as shown in FIG. 9D, the glass substrate (first substrate) 131 is removed, and each TFT element 1 is removed.
35 is isolated on a glass substrate (second substrate) 138.

【００６８】以下、第１実施の形態における図１(d)〜
図２(f)に示す手順によって、ＴＦＴパネル用の第３の
基板であるガラス基板の張り合わせ、ガラス基板(第２
の基板)１３８上のＴＦＴ素子１３５の第３の基板(パネ
ル用基板)上への選択転写を行うのである。Hereinafter, FIGS. 1 (d) to 1 (d) in the first embodiment will be described.
According to the procedure shown in FIG. 2 (f), a glass substrate as a third substrate for a TFT panel is laminated, and a glass substrate (second substrate) is bonded.
The TFT element 135 on the substrate 138 is selectively transferred onto the third substrate (panel substrate).

【００６９】上述のように、本実施の形態においては、
上記ガラス基板(第１の基板)１３１上に、Ｓi膜１３２
とＳi窒化膜(またはＳi酸化膜)１３３とで成る犠牲層１
２４を介してＴＦＴ素子１３５を素子分離溝１３６を隔
てて、ピッチｄx/ｍ,ｄy/ｎで形成する。ここで、ｄx,
ｄyは画素ドットの配列ピッチであり、ｍ,ｎは「２」以上
の自然数である。そして、ＴＦＴ素子１３５側にＵＶ剥
離樹脂１３７で第２の基板１３８を張り付けた後、Ｓi
との選択比が大きな選択エッチング液１３９を真空吸入
法でＴＦＴ素子分離溝１３６に充填して犠牲層１３４の
Ｓi窒化膜(あるいはＳi酸化膜)１３３のみを選択エッチ
ングし、ガラス基板(第１の基板)１３１を除去する。そ
うした後、第１実施の形態と同様にして、転写対象の
(つまり、画素を構成する)ＴＦＴ素子１３５のみを第３
の基板に選択転写するのである。As described above, in the present embodiment,
On the glass substrate (first substrate) 131, a Si film 132
Layer 1 composed of Si and Si nitride film (or Si oxide film) 133
The TFT elements 135 are formed at pitches dx / m and dy / n with the element isolation grooves 136 interposed therebetween. Where dx,
dy is the arrangement pitch of the pixel dots, and m and n are natural numbers of "2" or more. Then, after attaching the second substrate 138 to the TFT element 135 side with the UV release resin 137, Si
A selective etching solution 139 having a large selection ratio with the TFT substrate is filled in the TFT element isolation groove 136 by a vacuum suction method, and only the Si nitride film (or Si oxide film) 133 of the sacrifice layer 134 is selectively etched to form a glass substrate (first). The substrate 131 is removed. After that, similarly to the first embodiment, the transfer target
Only the TFT element 135 (that constitutes a pixel)
Selective transfer to the substrate.

【００７０】したがって、第１実施の形態と同じ効果を
奏する表示用トランジスタアレイパネルの形成方法を、
ガラス基板を上記第１の基板とする場合にも適用でき
る。ところで、第１の基板１３１としてガラス基板を用
いた場合には、通常は基板サイズに制限は無く大型の基
板を形成できる。したがって、ｄx/ｍ,ｄy/ｎのピッチ
でＴＦＴ素子１３５が形成された大型のガラス基板(第
１の基板)１３１を形成することによって、大型の表示
用トランジスタアレイパネルを容易に形成できるのであ
る。Therefore, a method of forming a display transistor array panel having the same effects as the first embodiment is described.
The present invention can be applied to a case where a glass substrate is used as the first substrate. By the way, when a glass substrate is used as the first substrate 131, the substrate size is usually not limited and a large substrate can be formed. Therefore, by forming a large glass substrate (first substrate) 131 on which the TFT elements 135 are formed at a pitch of dx / m, dy / n, a large display transistor array panel can be easily formed. .

【００７１】そして、本実施の形態においても、１枚の
第２の基板１３８を用いて、この第２の基板１３８から
第３の基板(パネル用基板)への選択転写を、第２の基板
１３８をｘ方向へｄx/ｍあるいはｙ方向へｄy/ｎだけ移
動させながら(ｍ×ｎ)枚の第３の基板に対して行うこと
によって、第１の基板１３１を１枚作成すれば、(ｍ×
ｎ)枚のパネル用基板に同一の選択転写を行うことがで
きる。すなわち、本実施の形態によれば、第１の基板１
３１上にＴＦＴ素子１３５を形成するコストを概略１/
(ｍ×ｎ)にできるのである。Also, in the present embodiment, the selective transfer from the second substrate 138 to the third substrate (panel substrate) is performed by using one second substrate 138. By performing 138 on (mxn) third substrates while moving 138 by dx / m in the x direction or dy / n in the y direction, if one first substrate 131 is formed, mx
n) The same selective transfer can be performed on the panel substrates. That is, according to the present embodiment, the first substrate 1
The cost of forming the TFT element 135 on the substrate 31 is approximately 1 /
(m × n).

【００７２】例えば、１３.３インチＸＧＡ(Extended G
raphics Array)−ＬＣＤ(液晶ディスプレイ)パネルに適
用した場合には、パネルサイズ２０３×２７０＝５４,
８１０mm2の中にＲＧＢ合計で７６８×１０２４＝２,３
５９,３００個のＴＦＴ素子を内蔵しており、ＴＦＴ素
子１３５の縦横夫々の配列ピッチｎは、概略８８μm,２
６４μmである。ここで、ｍ＝４,ｎ＝１２を選択して第
１の基板１３１上へのＴＦＴ素子１３５の配列ピッチを
２２μmとした場合には、ＴＦＴ素子１３５が全体転写
された第２の基板１３８上のＴＦＴ素子１３５の配列ピ
ッチは、表示用ＬＣＤパネルに比して縦４倍,横１２倍
であるために、１枚の第２の基板１２８から４×１２＝
４８枚の表示用ＬＣＤパネルを形成できる。したがっ
て、プロセスコストの大幅な削減を図ることができるの
である。For example, a 13.3 inch XGA (Extended G
raphics Array)-When applied to an LCD (liquid crystal display) panel, the panel size is 203 x 270 = 54,
Total of 768 × 1024 = 2,3 in RGB within 810 mm 2
59,300 TFT elements are built in, and the vertical and horizontal arrangement pitch n of the TFT elements 135 is approximately 88 μm, 2
64 μm. Here, when m = 4 and n = 12 are selected and the arrangement pitch of the TFT elements 135 on the first substrate 131 is set to 22 μm, on the second substrate 138 on which the entire TFT elements 135 are transferred. Since the arrangement pitch of the TFT elements 135 is 4 times longer and 12 times wider than that of the display LCD panel, 4 × 12 =
48 display LCD panels can be formed. Therefore, the process cost can be significantly reduced.

【００７３】こうして、本実施の形態においても、第１
実施の形態と同様に、表示用トランジスタアレイパネル
製造設備におけるイニシャルコストの約３０％を占める
成膜工程設備および約２６％を占めるフォト工程設備の
スループットを、実質的に１０倍〜１００倍程度向上さ
せることができる。また、ＴＦＴ素子４３の形成に要す
る材料費も１/１０〜１/１００に低減できる。結果とし
て、表示用トランジスタアレイパネルの製造コストの大
幅な削減が可能となるのである。Thus, also in the present embodiment, the first
Similar to the embodiment, the throughput of the film forming process equipment occupying about 30% of the initial cost and the photo processing equipment occupying about 26% of the initial cost in the display transistor array panel manufacturing equipment is substantially improved by about 10 to 100 times. Can be done. Further, the material cost required for forming the TFT element 43 can be reduced to 1/10 to 1/100. As a result, the manufacturing cost of the display transistor array panel can be significantly reduced.

【００７４】＜第３実施の形態＞上記各実施の形態にお
いては、一つの基板上のＴＦＴ素子の他の基板への選択
転写を、第２の基板４５,１３８から第３の基板４７へ
の転写に適用している。しかしながら、上記選択転写
は、第１の基板から第２の基板への転写に適用すること
も可能である。<Third Embodiment> In each of the above embodiments, the selective transfer of the TFT elements on one substrate to another substrate is performed by transferring the TFT elements from the second substrate 45, 138 to the third substrate 47. Applied to transcription. However, the above-described selective transfer can also be applied to transfer from the first substrate to the second substrate.

【００７５】すなわち、第１実施の形態における図１
(a)あるいは第２実施の形態における図９(a)と同様にし
て、第１の基板上に、画素の一方向への配列ピッチｄx
および他方向への配列ピッチｄyを「２」以上の自然数ｍ,
ｎで除した値ｄx/ｍ,ｄy/ｎのピッチで第１の基板上に
ＴＦＴ素子を１枚形成する。そして、上記１枚の第１の
基板から上記第２の基板上へのＴＦＴ素子の選択転写
を、アライメントを行って(ｍ×ｎ)回繰り返す。こうし
て、上記ＴＦＴ素子の上記一方向への配列ピッチがｄx
であり、他方向への配列ピッチがｄyであり、且つ、上
記第１の基板の大きさの(ｍ×ｎ)倍の大きさの第２の基
板を得るのである。以後は、この第２の基板上のＴＦＴ
素子を第３の基板上に全体転写すればよい。That is, FIG. 1 in the first embodiment
(a) Or in the same manner as in FIG. 9 (a) in the second embodiment, the arrangement pitch dx in one direction of pixels on the first substrate.
And the arrangement pitch dy in the other direction is a natural number m of 2 or more,
One TFT element is formed on the first substrate at a pitch of dx / m, dy / n divided by n. Then, the selective transfer of the TFT elements from the one first substrate to the second substrate is repeated (m × n) times with alignment. Thus, the arrangement pitch of the TFT elements in the one direction is dx
That is, the arrangement pitch in the other direction is dy, and the size of the second substrate is (m × n) times the size of the first substrate. After that, the TFT on this second substrate
The entire device may be transferred onto the third substrate.

【００７６】こうすることによって、上記第１の基板が
基板サイズに制限のあるＳi基板である場合でも、上記
制限を越えた大きさの表示用トランジスタアレイパネル
の形成が可能となるのである。上記第１の基板は、Ｓi
基板に限らずガラス基板であっても差し支えない。In this way, even if the first substrate is an Si substrate having a limited substrate size, it is possible to form a display transistor array panel having a size exceeding the above-mentioned limit. The first substrate is Si
Not limited to the substrate, a glass substrate may be used.

【００７７】尚、本実施の形態を適用する場合には、上
記第１の基板とＴＦＴ素子との間に形成される透明絶縁
膜下に、例えば、紫外線照射で接着力が低下するＵＶ硬
化型粘着剤等を形成して、上記第１の基板からＴＦＴ素
子を選択的に剥離可能にする必要がある。また、場合に
よっては、第３の基板への全体転写は無くとも構わな
い。In the case where this embodiment is applied, for example, a UV-curable type whose adhesive strength is reduced by ultraviolet irradiation under a transparent insulating film formed between the first substrate and the TFT element. It is necessary to form an adhesive or the like so that the TFT element can be selectively peeled off from the first substrate. In some cases, the entire transfer to the third substrate may not be performed.

【００７８】[0078]

【発明の効果】以上より明らかなように、請求項１に係
る発明の表示用トランジスタアレイパネルの形成方法
は、画素の一方向への配列ピッチｄx及び他方向への配
列ピッチｄyを２以上の自然数ｍ,ｎで除したｄx/ｍ,ｄy
/ｎのピッチで基板上に素子を設ける工程と、上記基板
上に設けられた素子のうち上記画素の配列ピッチｄx,ｄ
yに対応する素子のみを選択的に他の基板に転写する工
程を備えたので、転写元の基板上には、表示用トランジ
スタアレイパネルに形成される画素数の(ｍ×ｎ)倍の素
子が設けられている。したがって、上記転写元の１枚の
基板から(ｍ×ｎ)枚の表示用トランジスタアレイパネル
を形成することができる。As is apparent from the above description, the method of forming a display transistor array panel according to the first aspect of the present invention has an arrangement pitch dx in one direction and an arrangement pitch dy in another direction of two or more pixels. Dx / m, dy divided by natural numbers m, n
a step of providing elements on the substrate at a pitch of / n, and an arrangement pitch dx, d of the pixels among the elements provided on the substrate.
Since the method includes a step of selectively transferring only the element corresponding to y to another substrate, the element of (m × n) times the number of pixels formed on the display transistor array panel is provided on the transfer source substrate. Is provided. Accordingly, (m × n) display transistor array panels can be formed from one transfer source substrate.

【００７９】すなわち、この発明によれば、基板上への
素子形成コストを、基板上に形成される素子数と上記画
素数とが同数である従来の表示用トランジスタアレイパ
ネルの形成方法に比較して１/(ｍ×ｎ)に低減できる。
したがって、表示用トランジスタアレイパネル製造設備
におけるイニシャルコストの約３０％を占める成膜工程
設備および約２６％を占めるフォト工程設備のスループ
ットを、実質的に(ｍ×ｎ)倍に向上させることができ
る。また、上記素子の形成に要する材料費を１/(ｍ×
ｎ)に低減できる。結果として、表示用トランジスタア
レイパネルの製造コストの大幅な削減が可能となるので
ある。That is, according to the present invention, the cost of forming an element on a substrate is compared with the conventional method of forming a transistor array panel for display in which the number of elements formed on the substrate is the same as the number of pixels. 1 / (mxn).
Therefore, the throughput of the film forming process equipment occupying about 30% of the initial cost and the photo processing equipment occupying about 26% of the initial cost in the display transistor array panel manufacturing equipment can be substantially improved by (m × n) times. . Further, the material cost required for forming the above element is 1 / (mx ×
n). As a result, the manufacturing cost of the display transistor array panel can be significantly reduced.

【００８０】さらに、上記素子が設けられた１枚の基板
から他の基板上への素子の選択転写を(ｍ×ｎ)回繰り返
すことによって、上記素子の一方向への配列ピッチがｄ
xであり、他方向への配列ピッチがｄyであると共に、上
記転写元の基板の大きさの（ｍ×ｎ)倍の大きさの表示
用トランジタアレイパネルを得ることができる。したが
って、この場合には、上記従来の表示用トランジスタア
レイパネルの形成方法によって同じ大きさの表示用トラ
ンジスタアレイパネルを形成する場合に比較して、上記
素子の形成に要する材料費を低減できる。Further, the selective transfer of the element from one substrate provided with the element to another substrate is repeated (m × n) times, so that the arrangement pitch in one direction of the element is d.
x, the array pitch in the other direction is dy, and a display transistor array panel having a size (m × n) times the size of the transfer source substrate can be obtained. Therefore, in this case, the material cost required for forming the elements can be reduced as compared with the case where the display transistor array panel having the same size is formed by the above-described conventional method for forming the display transistor array panel.

【００８１】また、請求項２に係る発明の表示用トラン
ジスタアレイパネルの形成方法は、画素の一方向への配
列ピッチｄxおよび他方向への配列ピッチｄyを２以上の
自然数ｍ,ｎで除した値ｄx/ｍ,ｄy/ｎのピッチで第１の
基板上に素子を形成する工程と、上記第１の基板上に形
成された素子を第２の基板上に全体転写する工程と、上
記第１の基板を除去して上記素子を第２の基板上に孤立
配列させる工程と、記第２の基板上に転写された素子の
うち上記画素の配列ピッチｄx,ｄyに対応する素子のみ
を選択的に表示用トランジスタアレイ用の第３の基板に
転写する工程を備えたので、上記第１の基板上には、表
示用トランジスタアレイ用の第３の基板に形成される画
素数の(ｍ×ｎ)倍の素子が形成されている。したがっ
て、上記素子が形成された１枚の第１の基板から(ｍ×
ｎ)枚の第３の基板を形成することができる。In the method for forming a transistor array panel for display according to the present invention, the arrangement pitch dx in one direction of the pixels and the arrangement pitch dy in the other direction are divided by two or more natural numbers m and n. Forming elements on the first substrate at pitches of values dx / m and dy / n, transferring the entire elements formed on the first substrate onto the second substrate, Removing the one substrate and arranging the elements in isolation on the second substrate; and selecting only elements corresponding to the pixel arrangement pitches dx and dy among the elements transferred on the second substrate. Since the method includes a step of transferring to the third substrate for the display transistor array, the number of pixels formed on the third substrate for the display transistor array is (m × n) times as many elements are formed. Therefore, (mx × m) is obtained from one sheet of the first substrate on which the elements are formed.
n) third substrates can be formed.

【００８２】すなわち、この発明によれば、第１の基板
上への素子形成コストを、上記第１の基板上に形成され
る素子数と上記第３の基板に形成される画素数とが同数
である従来の表示用トランジスタアレイパネルの形成方
法に比較して１/(ｍ×ｎ)に低減できる。特に、上記第
１の基板がＳi基板である場合には、上記第１の基板上
に従来の１０倍〜１００倍の素子を形成することがで
き、表示用トランジスタアレイパネルの製造コストの大
幅な削減が可能となるのである。That is, according to the present invention, the cost of forming elements on the first substrate is reduced by the same number of elements formed on the first substrate and the number of pixels formed on the third substrate. Can be reduced to 1 / (m × n) as compared with the conventional method of forming a display transistor array panel. In particular, when the first substrate is a Si substrate, it is possible to form 10 to 100 times as many elements on the first substrate as in the prior art, which significantly reduces the manufacturing cost of the display transistor array panel. The reduction is possible.

【００８３】また、請求項３に係る発明の表示用トラン
ジスタアレイパネルの形成方法は、上記素子が選択転写
される基板上の位置には上記素子が嵌合される凹部が形
成されているので、上記凹部に接着剤層を形成すること
によって、上記素子の選択転写を更に容易に行うことが
できる。In the method of forming a display transistor array panel according to the third aspect of the present invention, a concave portion for fitting the element is formed at a position on the substrate where the element is selectively transferred. By forming the adhesive layer in the concave portion, the selective transfer of the element can be further easily performed.

【００８４】また、請求項４に係る発明の表示用トラン
ジスタアレイパネルの形成方法は、上記素子が選択転写
される基板上の位置に接着剤層が選択的に形成されてい
るので、上記素子の選択転写を更に容易に行うことがで
きる。In the method for forming a transistor array panel for display according to the present invention, the adhesive layer is selectively formed at a position on the substrate where the element is selectively transferred. Selective transfer can be performed more easily.

【００８５】また、請求項５に係る発明の表示用トラン
ジスタアレイパネルの形成方法における上記素子は順ス
タガ型のＴＦＴであるので、基板上への上記順スタガ型
ＴＦＴの形成コストを１/(ｍ×ｎ)に低減できる。In the method of forming a display transistor array panel according to the fifth aspect of the present invention, since the element is a forward staggered TFT, the cost of forming the forward staggered TFT on a substrate is reduced to 1 / (m × n).

【００８６】また、請求項６に係る発明の表示用トラン
ジスタアレイパネルの形成方法における上記素子は逆ス
タガ型のＴＦＴであるので、基板上への上記逆スタガ型
ＴＦＴの形成コストを１/(ｍ×ｎ)に低減できる。In the method for forming a transistor array panel for display according to the invention of claim 6, since the element is an inverted staggered TFT, the cost of forming the inverted staggered TFT on a substrate is 1 / (m × n).

【００８７】また、請求項７に係る発明の表示用トラン
ジスタアレイパネルの形成方法における上記素子はコプ
レーナ型のＴＦＴであるので、基板上への上記コプレー
ナ型ＴＦＴの形成コストを１/(ｍ×ｎ)に低減できる。In the method of forming a display transistor array panel according to the present invention, since the element is a coplanar TFT, the cost of forming the coplanar TFT on a substrate is reduced to 1 / (m × n). ).

【００８８】また、請求項８に係る発明の表示用トラン
ジスタアレイパネルの形成方法における上記素子は配線
交差部をも含んでいるので、基板上への上記配線交差部
をも含むＴＦＴの形成コストを１/(ｍ×ｎ)に低減でき
る。Further, in the method for forming a transistor array panel for display according to the present invention, since the element includes a wiring intersection, the cost of forming a TFT including the wiring intersection on a substrate is reduced. It can be reduced to 1 / (mxn).

【００８９】また、請求項９に係る発明の表示用トラン
ジスタアレイパネルの形成方法における上記第１の基板
はシリコン基板であるので上記素子を高密度に形成でき
る。したがって、上記自然数ｍ,ｎを容易に大きくする
ことが可能となり、上記第１の基板上への素子形成コス
トを大幅に低減できる。In the method of forming a transistor array panel for display according to the ninth aspect, the first substrate is a silicon substrate, so that the elements can be formed at a high density. Therefore, the natural numbers m and n can be easily increased, and the cost of forming an element on the first substrate can be significantly reduced.

【００９０】また、請求項１０に係る発明の表示用トラ
ンジスタアレイパネルの形成方法における上記第１の基
板はガラス基板であるので、上記第１の基板を大型に形
成できる。したがって、この発明によれば、上記第１の
基板上への素子形成コストを１/(ｍ×ｎ)に低減でき、
且つ、大型の表示用トランジスタアレイパネルを容易に
形成できる。In the method for forming a transistor array panel for display according to the tenth aspect of the present invention, since the first substrate is a glass substrate, the first substrate can be formed in a large size. Therefore, according to the present invention, the element formation cost on the first substrate can be reduced to 1 / (mxn),
In addition, a large display transistor array panel can be easily formed.

【００９１】また、請求項１１に係る発明の表示用トラ
ンジスタアレイパネルの形成方法では、上記第１の基板
上の素子の上記第２の基板上への全体転写を、光で接着
力が低下する接着剤によって行い、上記第２の基板上の
素子の上記第３の基板上への選択転写を、上記第２の基
板の裏面から転写対象の素子の箇所への選択的な光照射
によって行うので、上記接着剤の塗布および上記第２の
基板の裏面からの光の選択照射という簡単な方法によっ
て、上記第２の基板上の素子の上記第３の基板上への選
択転写を行うことできる。Further, in the method of forming a display transistor array panel according to the present invention, the entire transfer of the elements on the first substrate onto the second substrate is reduced by light. Since the selective transfer of the element on the second substrate onto the third substrate is performed by selective light irradiation from the back surface of the second substrate to the position of the element to be transferred. The element on the second substrate can be selectively transferred onto the third substrate by a simple method of applying the adhesive and selectively irradiating light from the back surface of the second substrate.

【００９２】また、請求項１２に係る発明の表示用トラ
ンジスタアレイパネルの形成方法では、上記第１の基板
上にフッ化水素酸に対して耐性を有する透明絶縁膜を形
成しているので、上記第１の基板の除去に際してエッチ
ャントとしてフッ化水素酸を使用する場合に、上記透明
絶縁膜の存在によって上記素子を保護できる。In the method for forming a display transistor array panel according to the twelfth aspect of the present invention, the transparent insulating film having resistance to hydrofluoric acid is formed on the first substrate. When hydrofluoric acid is used as an etchant when removing the first substrate, the device can be protected by the presence of the transparent insulating film.

【００９３】また、請求項１３に係る発明の表示用トラ
ンジスタアレイパネルの形成方法では、上記フッ化水素
酸に対して耐性を有する透明絶縁膜は酸化タンタル膜あ
るいはダイヤモンド膜の何れ一方であるので、上記第１
の基板除去用のエッチャントとしてフッ化水素酸が使用
する場合に、酸化タンタル膜あるいはダイヤモンド膜の
何れ一方の存在によって上記素子を確実に保護できる。In the method of forming a display transistor array panel according to the invention, the transparent insulating film having resistance to hydrofluoric acid is either a tantalum oxide film or a diamond film. The first
When hydrofluoric acid is used as an etchant for removing the substrate, the above element can be reliably protected by the presence of either the tantalum oxide film or the diamond film.

【図面の簡単な説明】[Brief description of the drawings]

【図１】この発明の表示用トランジスタアレイパネルの
形成方法における手順を示す図である。FIG. 1 is a view showing a procedure in a method for forming a display transistor array panel of the present invention.

【図２】図１に続く表示用トランジスタアレイパネルの
形成方法における手順を示す図である。FIG. 2 is a view showing a procedure in a method for forming a display transistor array panel following FIG. 1;

【図３】図２に続く受動素子部形成プロセスの説明図で
ある。FIG. 3 is an explanatory view of a passive element portion forming process following FIG. 2;

【図４】図１〜図３に示す形成方法によって形成された
表示用トランジスタアレイパネルの外観図である。FIG. 4 is an external view of a display transistor array panel formed by the forming method shown in FIGS.

【図５】順スタガＴＦＴの構造を示す図である。FIG. 5 is a diagram showing a structure of a forward staggered TFT.

【図６】逆スタガＴＦＴの構造を示す図である。FIG. 6 is a diagram showing a structure of an inverted staggered TFT.

【図７】コプレーナＴＦＴの構造を示す図である。FIG. 7 is a diagram showing a structure of a coplanar TFT.

【図８】逆スタガＴＦＴにおけるソース電極配線とゲー
ト電極配線との交差部の断面図である。FIG. 8 is a cross-sectional view of an intersection of a source electrode wiring and a gate electrode wiring in an inverted staggered TFT.

【図９】図１とは異なる表示用トランジスタアレイパネ
ルの形成方法における手順の一部を示す図である。FIG. 9 is a diagram showing a part of a procedure in a method for forming a display transistor array panel different from that in FIG. 1;

【図１０】従来の表示用トランジスタアレイパネルの形
成方法において剥離層をエッチング除去して第１の基板
全体を除去する方法の手順を示す図である。FIG. 10 is a view showing a procedure of a method for removing the entire first substrate by etching and removing a release layer in a conventional method for forming a transistor array panel for display.

【図１１】従来の表示用トランジスタアレイパネルの形
成方法においてエッチバック工程によって第１の基板全
体を除去する方法の手順を示す図である。FIG. 11 is a view showing a procedure of a method of removing the entire first substrate by an etch-back process in a conventional method of forming a display transistor array panel.

【図１２】従来の表示用トランジスタアレイパネルの形
成方法において中間エッチストップ層を用いたシリコン
薄膜転写法の手順を示す図である。FIG. 12 is a view showing a procedure of a silicon thin film transfer method using an intermediate etch stop layer in a conventional method for forming a display transistor array panel.

【図１３】従来の表示用トランジスタアレイパネルの形
成方法においてＵＶ剥離両面テープを用いた転写方法の
手順を示す図である。FIG. 13 is a view showing a procedure of a transfer method using a UV peeling double-sided tape in a conventional method for forming a display transistor array panel.

【図１４】従来の表示用トランジスタアレイパネルの形
成方法において基板上に密に形成したディバイスを粗に
配置し直す転写方法の手順を示す図である。FIG. 14 is a diagram showing a procedure of a transfer method in which devices densely formed on a substrate are coarsely arranged in a conventional method for forming a transistor array panel for display.

【符号の説明】[Explanation of symbols]

４１…Ｓi基板(第１の基板)、 ４２…Ｓi酸化
膜、４３,１２５…ＴＦＴ素子、 ４４,１２６
…素子分離溝、４５,１２８…ガラス基板(第２の基
板)、４６,１２７…ＵＶ剥離樹脂、 ４７,５５…
ガラス基板(第３の基板)、４８,５７…接着樹脂、
５０,６２…紫外線、６６…ソース電極配線、
６８…ゲート電極配線、６９…ドレイン電
極配線、 ７０…画素電極、１３１…ガラス基
板(第１の基板)、 １３２…Ｓi膜、１３３…Ｓi窒化膜
(あるいはＳi酸化膜)、１３４…犠牲層。41: Si substrate (first substrate), 42: Si oxide film, 43, 125: TFT element, 44, 126
... Element isolation groove, 45,128 ... Glass substrate (second substrate), 46,127 ... UV release resin, 47,55 ...
Glass substrate (third substrate), 48, 57 ... adhesive resin,
50, 62: ultraviolet rays, 66: source electrode wiring,
68: gate electrode wiring, 69: drain electrode wiring, 70: pixel electrode, 131: glass substrate (first substrate), 132: Si film, 133: Si nitride film
(Or Si oxide film), 134: sacrificial layer.

Claims (13)

【特許請求の範囲】[Claims] 【請求項１】 基板上に、画素の一方向への配列ピッチ
ｄxを２以上の自然数ｍで除したｄx/ｍのピッチ、およ
び、他方向への配列ピッチｄyを２以上の自然数ｎで除
したｄy/ｎのピッチで素子を設ける工程と、 上記基板上に設けられた素子のうち、上記画素の配列ピ
ッチｄx,ｄyに対応する素子のみを選択的に他の基板に
転写する工程を備えたことを特徴とする表示用トランジ
スタアレイパネルの形成方法。1. A pitch dx / m obtained by dividing an array pitch dx in one direction of a pixel by a natural number m of 2 or more, and an array pitch dy in another direction by a natural number n of 2 or more on a substrate. Providing the elements at a pitch of dy / n, and selectively transferring only the elements corresponding to the arrangement pitch dx, dy of the pixels among the elements provided on the substrate to another substrate. Forming a display transistor array panel. 【請求項２】 第１の基板上に、画素の一方向への配列
ピッチｄxを２以上の自然数ｍで除したｄx/ｍのピッ
チ、および、他方向への配列ピッチｄyを２以上の自然
数ｎで除したｄy/ｎのピッチで素子を形成する工程と、 上記第１の基板上に形成された素子を第２の基板上に全
体転写する工程と、 上記第１の基板を除去して、上記素子を上記第２の基板
上に孤立配列させる工程と、 上記第２の基板上に転写された素子のうち、上記画素の
配列ピッチｄx,ｄyに対応する素子のみを選択的に表示
用トランジスタアレイ用の第３の基板に転写する工程を
備えたことを特徴とする表示用トランジスタアレイパネ
ルの形成方法。2. A pitch of dx / m obtained by dividing an array pitch dx in one direction of a pixel by a natural number m of 2 or more on the first substrate, and a natural number of 2 or more in an array pitch dy in another direction. forming an element at a pitch of dy / n divided by n, transferring the entire element formed on the first substrate onto a second substrate, and removing the first substrate Arranging the elements in isolation on the second substrate; and selectively displaying only elements corresponding to the pixel arrangement pitches dx and dy among the elements transferred on the second substrate. A method for forming a transistor array panel for display, comprising a step of transferring to a third substrate for a transistor array. 【請求項３】 請求項１あるいは請求項２に記載の表示
用トランジスタアレイパネルの形成方法において、 上記素子が選択転写される基板上の位置には、上記素子
が嵌合される凹部が形成されていることを特徴とする表
示用トランジスタアレイパネルの形成方法。3. The method for forming a display transistor array panel according to claim 1, wherein a concave portion is formed at a position on the substrate where the element is selectively transferred. Forming a display transistor array panel. 【請求項４】 請求項１あるいは請求項２に記載の表示
用トランジスタアレイパネルの形成方法において、 上記素子が選択転写される基板上の位置には、接着剤層
が選択的に形成されていることを特徴とする表示用トラ
ンジスタアレイパネルの形成方法。4. The method for forming a transistor array panel for display according to claim 1, wherein an adhesive layer is selectively formed at a position on the substrate where the element is selectively transferred. A method for forming a display transistor array panel, comprising: 【請求項５】 請求項１あるいは請求項２に記載の表示
用トランジスタアレイパネルの形成方法において、 上記素子は、順スタガ型の薄膜トランジスタであること
を特徴とする表示用トランジスタアレイパネルの形成方
法。5. The method for forming a display transistor array panel according to claim 1, wherein the element is a forward staggered thin film transistor. 【請求項６】 請求項１あるいは請求項２に記載の表示
用トランジスタアレイパネルの形成方法において、 上記素子は、逆スタガ型の薄膜トランジスタであること
を特徴とする表示用トランジスタアレイパネルの形成方
法。6. The method of forming a display transistor array panel according to claim 1, wherein the element is an inverted staggered thin film transistor. 【請求項７】 請求項１あるいは請求項２に記載の表示
用トランジスタアレイパネルの形成方法において、 上記素子は、コプレーナ型の薄膜トランジスタであるこ
とを特徴とする表示用トランジスタアレイパネルの形成
方法。7. The method of forming a display transistor array panel according to claim 1, wherein the element is a coplanar thin film transistor. 【請求項８】 請求項５乃至請求項７の何れか一つに記
載の表示用トランジスタアレイパネルの形成方法におい
て、 上記素子は、配線交差部をも含んでいることを特徴とす
る表示用トランジスタアレイパネルの形成方法。8. The method for forming a display transistor array panel according to claim 5, wherein the element includes a wiring intersection. A method for forming an array panel. 【請求項９】 請求項２に記載の表示用トランジスタア
レイパネルの形成方法において、 上記第１の基板はシリコン基板であることを特徴とする
表示用トランジスタアレイパネルの形成方法。9. The method for forming a display transistor array panel according to claim 2, wherein the first substrate is a silicon substrate. 【請求項１０】 請求項２に記載の表示用トランジスタ
アレイパネルの形成方法において、 上記第１の基板はガラス基板であることを特徴とする表
示用トランジスタアレイパネルの形成方法。10. The method for forming a transistor array panel for display according to claim 2, wherein the first substrate is a glass substrate. 【請求項１１】 請求項２に記載の表示用トランジスタ
アレイパネルの形成方法において、 上記第１の基板上の素子の上記第２の基板上への全体転
写は、光によって接着力が低下する接着剤によって行
い、 上記第２の基板上の素子の上記第３の基板上への選択転
写は、上記第２の基板の裏面から上記画素の配列ピッチ
ｄx,ｄyに対応する素子の箇所への光照射によって転写
の対象となる素子のみを選択的に上記第２の基板から剥
離することによって行うことを特徴とする表示用トラン
ジスタアレイパネルの形成方法。11. The method for forming a transistor array panel for display according to claim 2, wherein the entire transfer of the elements on the first substrate to the second substrate is performed by bonding whose adhesive strength is reduced by light. The selective transfer of the elements on the second substrate onto the third substrate is performed by light from the back surface of the second substrate to the locations of the elements corresponding to the pixel pitches dx and dy. A method for forming a display transistor array panel, which is performed by selectively peeling only elements to be transferred by irradiation from the second substrate. 【請求項１２】 請求項２に記載の表示用トランジスタ
アレイパネルの形成方法において、 上記第１の基板上にフッ化水素酸に対して耐性を有する
透明絶縁膜を形成し、この透明絶縁膜上に上記素子を形
成することを特徴とする表示用トランジスタアレイパネ
ルの形成方法。12. The method for forming a transistor array panel for display according to claim 2, further comprising: forming a transparent insulating film having resistance to hydrofluoric acid on the first substrate; A method for forming a transistor array panel for display, comprising forming the above-mentioned element on a substrate. 【請求項１３】 請求項１２に記載の表示用トランジス
タアレイパネルの形成方法において、 上記フッ化水素酸に対して耐性を有する透明絶縁膜は、
酸化タンタル膜あるいはダイヤモンド膜の何れ一方であ
ることを特徴とする表示用トランジスタアレイパネルの
形成方法。13. The method for forming a transistor array panel for display according to claim 12, wherein the transparent insulating film having resistance to hydrofluoric acid comprises:
A method for forming a transistor array panel for display, which is either a tantalum oxide film or a diamond film.
JP31029997A 1997-11-12 1997-11-12 Method of forming transistor array panel for display Expired - Fee Related JP3406207B2 (en)

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