JPH1079471A - Semiconductor device, its manufacture and flexible card - Google Patents
Semiconductor device, its manufacture and flexible cardInfo
- Publication number
- JPH1079471A JPH1079471A JP23501696A JP23501696A JPH1079471A JP H1079471 A JPH1079471 A JP H1079471A JP 23501696 A JP23501696 A JP 23501696A JP 23501696 A JP23501696 A JP 23501696A JP H1079471 A JPH1079471 A JP H1079471A
- Authority
- JP
- Japan
- Prior art keywords
- thickness
- semiconductor device
- layer
- divided
- substrate
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
Landscapes
- Mechanical Treatment Of Semiconductor (AREA)
- Semiconductor Integrated Circuits (AREA)
Abstract
Description
【０００１】[0001]
【発明の属する技術分野】本発明は、ＩＣカード又はマ
ルチチップモジュール等に用いる半導体装置、その製造
方法及びフレキシブルカードに関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device used for an IC card or a multi-chip module, a method for manufacturing the same, and a flexible card.
【０００２】[0002]
【従来の技術】ＩＣカードに代表される薄型、軽量の高
機能電子装置は、その利便性のため需要が急増し応用分
野が拡大している。ＩＣカードには電気信号や電源を接
触式で得る方式と非接触式で得る方式があり、特に後者
は高周波結合のためコンタクト部に係わる不良がなく、
静電気に強い特徴がある。従来のＩＣカードの構造は、
「ＩＣカード」第３３頁（社団法人電子情報通信学会
編、オーム社発行、第１版、１９９０年５月２５日発
行）に記載されており、薄いＬＳＩを使用したＩＣカー
ドについては特開平３−８７２９９号公報や特開平７−
９９２６７号公報に記載がある。2. Description of the Related Art Thin and lightweight high-performance electronic devices represented by IC cards are rapidly increasing in demand due to their convenience, and their application fields are expanding. There are two types of IC cards: a method of obtaining electric signals and power by a contact method and a method of obtaining a non-contact method.
There is a feature that is strong against static electricity. The structure of a conventional IC card is
"IC Card" is described on page 33 (edited by the Institute of Electronics, Information and Communication Engineers, issued by Ohmsha, 1st edition, issued on May 25, 1990). -87299 and JP-A-7-
No. 99267 discloses this.
【０００３】図８は従来のＩＣカードの主要部分の構成
を示す断面構造図である。ＬＳＩチップ８１とコンデン
サチップ８２はワイヤ８８によって接続され、これがＩ
Ｃカード全体を構成する樹脂フィルム８３、８７とコア
層８５に接着層８４、８６によって固定されている。FIG. 8 is a sectional structural view showing the structure of a main part of a conventional IC card. The LSI chip 81 and the capacitor chip 82 are connected by a wire 88.
It is fixed to resin films 83 and 87 and a core layer 85 constituting the entire C card by adhesive layers 84 and 86.
【０００４】ＬＳＩチップの厚みが厚いと機械的変形に
強い反面、折れ曲がりに弱い傾向があり、カードを曲げ
たり、ねじったりしてもＬＳＩが壊れない構造の検討が
続けられている。このような中で基板厚さが極めて薄い
ＬＳＩをカードの厚さ方向の中央である中立面に実装す
る構造が特開平７−９９２６７号公報に記載されてお
り、この構造は曲げやねじりに強い特徴がある。そのた
め今後のＩＣカードの技術はこれと電気信号や電源の非
接触方式を組合せた構成が主流になるものと考えられて
いる。この非接触式ＩＣカードを以下フレキシブルＩＣ
カード、略してＦカードと呼ぶ。これには薄型ＬＳＩの
他に薄型コンデンサ及び薄型コイルのデバイスが必要で
ある。Ｆカードに用いるＬＳＩやコンデンサ等のチップ
厚さは、１００μｍ以下の薄型が要求され、また非接触
式ＩＣカードには３０ｎＦ程度の大容量コンデンサが使
われる。When the thickness of the LSI chip is large, it is strong against mechanical deformation, but is liable to bend. Therefore, a structure in which the LSI is not broken even if the card is bent or twisted has been studied. Japanese Patent Laid-Open No. 7-99267 discloses a structure in which an LSI having an extremely thin substrate is mounted on a neutral surface at the center in the thickness direction of the card. There are strong features. For this reason, it is considered that the future technology of IC cards will be mainly composed of a combination of this and a non-contact method of an electric signal or a power supply. This non-contact IC card is referred to as a flexible IC
The card is called F card for short. This requires a thin capacitor and a thin coil device in addition to a thin LSI. Chips such as LSIs and capacitors used for F-cards are required to be as thin as 100 μm or less, and large-capacity capacitors of about 30 nF are used for non-contact IC cards.
【０００５】[0005]
【発明が解決しようとする課題】従来、通常用いられて
いるＩＣカードのＬＳＩチップやコンデンサチップの基
板の厚さは図８のようにＩＣカードの厚さよりも薄く、
チップの強度を保つために約２００μｍ程度の厚さのも
のが使われている。一方、Ｆカード用のチップとして
は、基板厚さが１００μｍ以下の薄いものを用いること
が好ましい。Conventionally, the substrate of the LSI chip or the capacitor chip of the IC card which is usually used is thinner than the thickness of the IC card as shown in FIG.
A chip having a thickness of about 200 μm is used to maintain the strength of the chip. On the other hand, it is preferable to use a thin chip having a substrate thickness of 100 μm or less as an F card chip.
【０００６】例えば、Ｓｉ単結晶基板上に約３００の比
誘電率を持つＢＳＴ（ＢａＴｉＯ3とＳｒＴｉＯ3の混晶
体）誘電体薄膜を用いてコンデンサを形成したとする
と、Ｓｉ単結晶基板の厚さが約２００μｍの構造ではウ
エーハの反りは小さいが、これを約５０μｍの基板厚さ
に加工するとＳｉ単結晶基板上の成膜層によってウエー
ハの反りは非常に大きくなる。For example, if a capacitor is formed on a Si single crystal substrate using a BST (BaTiO 3 and SrTiO 3 mixed crystal) dielectric thin film having a relative dielectric constant of about 300, the thickness of the Si single crystal substrate Although the warp of the wafer is small in a structure of about 200 μm, when the wafer is processed to a substrate thickness of about 50 μm, the warp of the wafer becomes extremely large due to the film formation layer on the Si single crystal substrate.
【０００７】そのため上記のようなＩＣカード用の積層
コンデンサが形成されたウエーハを薄くすると、製造プ
ロセスの途中やチップに加工するときにウエーハが割れ
やすく、チップの製造歩留まりが低いという問題があっ
た。さらに得られたチップをＩＣカードに実装する際に
もチップの反りが大きいために取り扱いにくく、割れた
り、組立歩留まりが低いという問題があった。Therefore, when the wafer on which the multilayer capacitor for an IC card is formed as described above is made thin, the wafer is liable to be broken during the manufacturing process or processing into a chip, resulting in a low chip manufacturing yield. . Further, when the obtained chip is mounted on an IC card, there is a problem that it is difficult to handle the chip due to a large warpage of the chip, cracks and a low assembly yield.
【０００８】本発明の第１の目的は、大量生産に適し、
取り扱いやすく、組立歩留まりが良好な、基板の薄い半
導体装置を提供することにある。本発明の第２の目的
は、そのような半導体装置を容易に製造することのでき
る半導体装置の製造方法を提供することにある。本発明
の第３の目的は、そのような半導体装置を有するフレキ
シブルカードを提供することにある。A first object of the present invention is suitable for mass production,
An object of the present invention is to provide a semiconductor device having a thin substrate, which is easy to handle and has a good assembly yield. A second object of the present invention is to provide a method of manufacturing a semiconductor device that can easily manufacture such a semiconductor device. A third object of the present invention is to provide a flexible card having such a semiconductor device.
【０００９】[0009]
【課題を解決するための手段】上記第１の目的を達成す
るために、本発明の半導体装置は、厚さが１μｍから１
００μｍの範囲にある半導体基板と、この半導体基板に
配置された素子を有し、この素子を構成する成膜層の内
の少なくとも一層を分割し、分割された各素子を並列に
接続するようにしたものである。In order to achieve the first object, a semiconductor device according to the present invention has a thickness of 1 μm to 1 μm.
A semiconductor substrate in the range of 00 μm, and an element disposed on the semiconductor substrate, at least one of the film forming layers constituting the element is divided, and the divided elements are connected in parallel. It was done.
【００１０】半導体基板は、Ｓｉ単結晶基板であること
が好ましい。結晶欠陥の少ないＳｉ単結晶基板は１μｍ
から１００μｍの厚さになっても強靭であり、極端に曲
げない限り割れない特徴があるためである。さらに強靭
な半導体基板であるためには、その厚さを１０μｍから
１００μｍの範囲とすることがより好ましい。Preferably, the semiconductor substrate is a Si single crystal substrate. 1 μm Si single crystal substrate with few crystal defects
This is because it is tough even at a thickness of from 100 μm to 100 μm and does not crack unless it is extremely bent. For a tougher semiconductor substrate, the thickness is more preferably in the range of 10 μm to 100 μm.
【００１１】また、上記第２の目的を達成するために、
本発明の半導体装置の製造方法は、半導体基板上に複数
の成膜層からなる素子を形成し、この素子を構成する成
膜層の内の少なくとも一層を分割し、分割された各素子
を並列に接続するための配線層の少なくとも一部を形成
し、半導体基板の裏面を研磨してその厚さを１μｍから
１００μｍ範囲の厚さとしたものである。In order to achieve the second object,
In the method for manufacturing a semiconductor device according to the present invention, an element including a plurality of film layers is formed on a semiconductor substrate, at least one of the film layers forming the element is divided, and the divided elements are arranged in parallel. At least a part of a wiring layer for connection to the semiconductor substrate is formed, and the back surface of the semiconductor substrate is polished to a thickness in a range of 1 μm to 100 μm.
【００１２】上記の半導体基板の裏面の研磨は、機械的
研磨を行って後に化学的研磨を行うことが好ましい。In the polishing of the back surface of the semiconductor substrate, it is preferable to perform mechanical polishing and then to perform chemical polishing.
【００１３】また、上記第３の目的を達成するために、
本発明のフレキシブルカードは、上記のいずれかの半導
体装置と、この半導体装置を内部に配置したフレキシブ
ルな構造材から構成するようにしたものである。Further, in order to achieve the third object,
A flexible card according to the present invention includes any one of the above-described semiconductor devices and a flexible structural member having the semiconductor device disposed therein.
【００１４】上記のように素子を分割したとき、ウエー
ハの反りが小さくなることを図２、図３にその一例を示
して説明する。図３は、素子が誘電体薄膜を金属で挟ん
だ構造のメタル−絶縁体−メタル型（ＭＩＭ；Ｍｅｔａ
ｌ−Ｉｎｓｕｌａｔｏｒ−Ｍｅｔａｌ型）コンデンサで
あるときのその主要部の断面構成図であり、図２はその
平面図である。Ｓｉ単結晶基板１上のＳｉＯ2層２の上
に、下部電極層３、ＢＳＴの高誘電体層４、上部電極層
５が積層されたコンデンサ部２１が設けられている。チ
ップ２０の間に当たる位置にはスクライブ領域２９があ
り、コンデンサ部２１の実効面積（Ｌｘ×Ｌｙ）は約２
×２ｍｍ2である。コンデンサ部２１は縦、横共に４個
に分割され、１６個のセル２６からなる。分割した１個
のセル２６のサイズは約５００×５００μｍ2である。
分割の幅は５μｍである。Ｓｉ単結晶基板上の成膜層の
応力が分断し、基板厚さ（Ｔｓｎ）を極めて薄くした厚
さ（Ｔｓｔ）としてもウエーハ上での応力が分散し、反
りが小さく抑えられる。The fact that the warpage of the wafer is reduced when the element is divided as described above will be described with reference to FIGS. FIG. 3 shows a metal-insulator-metal type (MIM; Meta) structure in which an element has a dielectric thin film sandwiched between metals.
FIG. 2 is a cross-sectional configuration view of a main part when the capacitor is an (l-insulator-metal type) capacitor, and FIG. 2 is a plan view thereof. On the SiO 2 layer 2 on the Si single crystal substrate 1, there is provided a capacitor section 21 in which a lower electrode layer 3, a high dielectric layer 4 of BST, and an upper electrode layer 5 are laminated. A scribe region 29 is provided at a position between the chips 20, and an effective area (Lx × Ly) of the capacitor unit 21 is about 2
× 2 mm 2 . The capacitor unit 21 is divided into four in both the vertical and horizontal directions, and includes 16 cells 26. The size of one divided cell 26 is about 500 × 500 μm 2 .
The width of the division is 5 μm. The stress of the film formation layer on the Si single crystal substrate is divided, and even when the substrate thickness (Tsn) is made extremely thin (Tst), the stress on the wafer is dispersed, and the warpage is suppressed to be small.
【００１５】基板厚さに対応した、好ましい分割の基準
を以下に示す。一般に、ウエーハの反り量Ｒは式（１）
の関係によって記述される。 Ｒ＝Ｋ・Ｓｆ・Ｔｆ・Ｄ2／Ｔｓ2 （１） ここで、Ｓｆ：成膜の応力、Ｔｆ：成膜の厚さ、Ｄ：ウ
エーハの直径 Ｔｓ：基板の厚さ、Ｋ：常数、である。Preferred division criteria corresponding to the substrate thickness are shown below. In general, the amount of wafer warpage R is given by the following equation (1).
Described by the relationship R = K · Sf · Tf · D 2 / Ts 2 (1) where, Sf: stress of film formation, Tf: thickness of film formation, D: diameter of wafer Ts: thickness of substrate, K: constant number, It is.
【００１６】従来構造の基板厚さ（Ｔｓｎ）のものを薄
型の厚さ（Ｔｓｔ）に仕上げるとウエーハの反り量Ｒは
式（１）の関係によって、ウエーハ直径の２乗と厚さの
１／２乗倍で大きくなる。ウエーハ直径が一定のとき、
素子サイズの面積が大きい程反りも大きい。このため薄
いウエーハで反りを小さくするためには、デバイスを構
成する成膜層からなる素子を細かく分割し応力の分散を
図るのが好ましい。薄型の厚さ（Ｔｓｔ）のウエーハの
反り量を従来構造の基板厚さ（Ｔｓｎ）程度の反り量以
下にするためには、素子をいくつかのセルに分割し、そ
のセルの縦、横一辺の長さをいずれも半導体基板の厚さ
の１倍から２０倍の範囲とすることが好ましい。分割し
たセルの形状は４角形でなくて、多角形や楕円形等でも
よい。このときの大きさは上記した最大の大きさより小
さく、最小の大きさより大きければよい。一辺の長さは
半導体基板の厚さの１倍未満であっても反り量は問題な
いが、より複雑な構成になるので１倍以上が好ましい。When the substrate having the conventional structure (Tsn) is finished to a thin thickness (Tst), the amount of warpage R of the wafer is calculated by the relation of the equation (1), and the square of the wafer diameter and 1 / th of the thickness is obtained. It increases by the square. When the wafer diameter is constant,
The larger the area of the element size, the greater the warpage. For this reason, in order to reduce the warpage with a thin wafer, it is preferable to divide the element formed of the film forming layer constituting the device into small pieces to disperse the stress. In order to reduce the amount of warpage of a wafer having a thin thickness (Tst) to be equal to or less than the amount of warpage of the substrate thickness (Tsn) of the conventional structure, the element is divided into several cells, and one side of the cell is arranged vertically and horizontally. Is preferably in the range of 1 to 20 times the thickness of the semiconductor substrate. The shape of the divided cells is not limited to a quadrangle, but may be a polygon or an ellipse. The size at this time may be smaller than the above-described maximum size and larger than the minimum size. Even if the length of one side is less than one time the thickness of the semiconductor substrate, there is no problem in the amount of warpage, but since the structure becomes more complicated, it is preferably one time or more.
【００１７】例えばコンデンサの実効面積（チップ面積
にほぼ同じ）が２ｍｍ×２ｍｍの場合、半導体基板の厚
さを５０μｍとすれば、一辺が５０μｍから１０００μ
ｍに分割すればよい。For example, when the effective area of the capacitor (substantially the same as the chip area) is 2 mm × 2 mm, if the thickness of the semiconductor substrate is 50 μm, one side is 50 μm to 1000 μm.
m.
【００１８】分割する成膜層は必ずしもＳｉ単結晶基板
上に形成した全層である必要がなく応力の大きな層だけ
でもよい。Ｆカード用の薄型ＬＳＩチップや薄型コンデ
ンサチップは上記基準でパターンのレイアウトを行い、
従来の基板厚さの素子と同じ製造条件で製造できるので
プロセスの共通化が図れ、低コスト化できる。The divided film layers need not necessarily be all layers formed on the Si single crystal substrate, but may be only layers having a large stress. For the thin LSI chip and thin capacitor chip for F card, the pattern layout is performed based on the above criteria.
Since the device can be manufactured under the same manufacturing conditions as the conventional device having a substrate thickness, the process can be shared and the cost can be reduced.
【００１９】[0019]
〈実施例１〉本発明の一実施例であるＭＩＭ型コンデン
サのチップ２０の平面図と断面構造図を図２、図３に示
す。Ｓｉ単結晶基板１上にＳｉＯ2層２を約５００ｎｍ
の厚みに形成し、これに重ねてＴｉ−Ｐｔの下部電極層
３、ＢＳＴの高誘電体層４、Ｔｉ−Ｐｔ−Ａｕの上部電
極層５を順次形成する。これらの膜厚はこの順番に約２
００、３００、３００ｎｍである。チップ間にはスクラ
イブ領域２９があり、コンデンサ部２１の実効面積（Ｌ
ｘ×Ｌｙ）は約２×２ｍｍ2である。<Embodiment 1> FIGS. 2 and 3 are a plan view and a sectional structural view of a chip 20 of an MIM type capacitor according to an embodiment of the present invention. An SiO 2 layer 2 of about 500 nm is formed on a Si single crystal substrate 1.
The lower electrode layer 3 of Ti-Pt, the high dielectric layer 4 of BST, and the upper electrode layer 5 of Ti-Pt-Au are sequentially formed thereon. These film thicknesses are about 2 in this order.
00, 300, and 300 nm. There is a scribe area 29 between the chips, and the effective area (L
x × Ly) is about 2 × 2 mm 2 .
【００２０】コンデンサ部２１は縦、横共に４個に分割
され、１６個のセル２６からなる。分割した１個のセル
２６のサイズは約５００×５００μｍ2である。分割の
幅は５μｍ以下で十分であり、チップ面積の変化にほと
んど影響を与えない。ＳｉＯ2層２はセルとして分割し
なくてもよい。なお、コンデンサの引き出し電極やボン
デングパッド部は同図の記載から省略した。The capacitor section 21 is divided into four cells both vertically and horizontally, and is composed of 16 cells 26. The size of one divided cell 26 is about 500 × 500 μm 2 . A division width of 5 μm or less is sufficient, and has little effect on changes in chip area. The SiO 2 layer 2 does not have to be divided as cells. The extraction electrodes and the bonding pad portion of the capacitor are omitted from the illustration in FIG.
【００２１】分割した１個のセルの詳細を図４に示し、
分割の方法を説明する。Ｓｉ単結晶基板１上のＳｉＯ2
層２上に形成されたＴｉ−Ｐｔの下部電極層４３、ＢＳ
Ｔの高誘電体層４４、Ｔｉ−Ｐｔ−Ａｕの上部電極層４
５を以下の方法で分割してセルの構造を形成する。ウエ
ーハ全面にＭＩＭ型構造を形成した後、ホトレジスト層
をマスクにイオンミリングによって上部電極層４５を除
去し、分割する。このとき上記のスクライブ領域２９も
除去される。さらに順次同じ手法で高誘電体層４４、下
部電極層４３を除去する。FIG. 4 shows the details of one divided cell.
The method of division will be described. SiO 2 on Si single crystal substrate 1
Ti-Pt lower electrode layer 43 formed on layer 2, BS
T high dielectric layer 44, Ti-Pt-Au upper electrode layer 4
5 is divided by the following method to form a cell structure. After the MIM type structure is formed on the entire surface of the wafer, the upper electrode layer 45 is removed by ion milling using the photoresist layer as a mask and divided. At this time, the scribe area 29 is also removed. Further, the high dielectric layer 44 and the lower electrode layer 43 are sequentially removed by the same method.
【００２２】次ぎに表面にＳｉＯ2絶縁膜４６を形成
し、上部電極層４５と下部電極層４３に達する導通孔を
加工し、配線層４７、４８を形成する。分割したセルは
下部電極用の配線層４７と上部電極用の配線層４８によ
って並列に接続され、全体で大容量のコンデンサとな
る。また、表面にはＢＳＴの高誘電体層４４を外部環境
から保護する目的でＳｉＮ膜とＳｉＯ2膜からなる保護
膜４９を形成する。保護膜４９はＡｌＮ又はＡｌ2Ｏ3か
らなる絶縁材料であってもよい。分割する成膜層はＢＳ
Ｔの高誘電体層の応力が大きいので、これと上部電極だ
けであってもよい。Next, a SiO 2 insulating film 46 is formed on the surface, and conduction holes reaching the upper electrode layer 45 and the lower electrode layer 43 are processed to form wiring layers 47 and 48. The divided cells are connected in parallel by a wiring layer 47 for the lower electrode and a wiring layer 48 for the upper electrode, and a large-capacity capacitor as a whole is obtained. On the surface, a protective film 49 made of a SiN film and a SiO 2 film is formed for the purpose of protecting the BST high dielectric layer 44 from the external environment. The protective film 49 may be an insulating material made of AlN or Al 2 O 3 . The divided film layer is BS
Since the stress of the high dielectric layer of T is large, only the high dielectric layer and the upper electrode may be used.
【００２３】続いて約５００μｍの厚さのＳｉ単結晶基
板１の裏面側から約１８０μｍまでＳｉを研削除去し、
さらにＨＦとＨＮＯ3を主成分とした化学エッチング液
によってＳｉを溶解し、約４０μｍの基板厚さにする。
研削でＳｉ単結晶内に生じた損傷は約４０μｍ以上の量
の化学エッチングで完全に除去できる。これによって約
４０μｍの厚さのＳｉ単結晶基板上にＭＩＭ型薄型コン
デンサが製造される。Subsequently, Si is ground and removed to about 180 μm from the back side of the Si single crystal substrate 1 having a thickness of about 500 μm,
Further, Si is dissolved by a chemical etching solution containing HF and HNO 3 as main components, so that the substrate thickness is about 40 μm.
Damage caused in the Si single crystal by grinding can be completely removed by chemical etching of about 40 μm or more. As a result, an MIM type thin capacitor is manufactured on a Si single crystal substrate having a thickness of about 40 μm.
【００２４】従来構造の分割しない一体面積のコンデン
サの場合、基板厚さ（Ｔｓｎ）が約２００μｍでウエー
ハの反り量Ｒｎは２０μｍであった。これを基板厚さ
（Ｔｓｔ）の４０μｍの薄型にするとウエーハの反り量
Ｒｔは約５００μｍと大きな値になって取り扱い上問題
であった。本実施例では、従来と同じ容量値で４０μｍ
の基板厚さ（Ｔｓｔ）のウエーハの反り量Ｒｎが２０μ
ｍの値を越えないようにするためには、従来構造のチッ
プ内の最大セルサイズ（Ｌｘ、Ｌｙ）を縦、横とも基板
の厚み（４０μｍ）の２０倍以下、１倍以上に分割する
とよい。本実施例では縦、横とも４個に分割し（分割
数；ｎ＝４）、１個のセル２６のサイズ（Ｌｘ／ｎ、Ｌ
ｙ／ｎ）は約５００×５００μｍ2とした。なお、セル
２６のサイズとは、分割された各層の内の最も大きな層
のサイズ（本実施例では下部電極層４３のサイズ）とす
る。この後、ウエーハからチップを切り出し、特性の揃
ったＭＩＭ型薄型コンデンサを大量に生産することがで
きる。In the case of the conventional capacitor having an undivided integral area, the substrate thickness (Tsn) is about 200 μm and the amount of warpage Rn of the wafer is 20 μm. If this is made as thin as 40 μm of the substrate thickness (Tst), the warpage Rt of the wafer becomes a large value of about 500 μm, which is a problem in handling. In this embodiment, the same capacitance value as that of the related art
Wafer warpage Rn of substrate thickness (Tst) of 20 μm
In order not to exceed the value of m, the maximum cell size (Lx, Ly) in the chip having the conventional structure is preferably divided into 20 times or less and 1 or more times the thickness (40 μm) of the substrate in both the vertical and horizontal directions. . In the present embodiment, the cell is divided into four in both the vertical and horizontal directions (the number of divisions; n = 4), and the size (Lx / n, L
y / n) was about 500 × 500 μm 2 . The size of the cell 26 is the size of the largest layer among the divided layers (the size of the lower electrode layer 43 in this embodiment). Thereafter, chips are cut out from the wafer, and mass-produced MIM thin capacitors having uniform characteristics can be produced.
【００２５】本実施例で得られたチップをＦカードに実
装すると、チップの反り量が小さいため、従来構造の分
割しない一体面積のコンデンサを有するチップで基板厚
さの４０μｍのチップをＦカードに実装する場合に比べ
て組立歩留まりが大幅に向上した。When the chip obtained in this embodiment is mounted on an F card, since the amount of warpage of the chip is small, a chip having a capacitor of a conventional structure and having an integral area which is not divided and having a substrate thickness of 40 μm is mounted on the F card. The assembly yield has been greatly improved compared to mounting.
【００２６】〈実施例２〉本発明の他の実施例であるセ
ルの構造断面図を図５に示す。これはホトマスク数を減
らして製造工程を簡略することを目的としたものでセル
の分割は実施例１で述べた主旨と同じである。図４と異
なる点だけを述べると１回のホトレジスト層をマスクに
イオンミリングによって高誘電体層５４と下部電極層５
３を形成すること、下部電極用の配線層５７は下部電極
層５３の側面と主に接触して導通することである。<Embodiment 2> FIG. 5 is a sectional view showing the structure of a cell according to another embodiment of the present invention. This is intended to simplify the manufacturing process by reducing the number of photomasks, and the division of the cells is the same as the purpose described in the first embodiment. The only difference from FIG. 4 is that the high dielectric layer 54 and the lower electrode layer 5 are formed by ion milling using one photoresist layer as a mask.
Forming 3 means that the lower electrode wiring layer 57 is mainly in contact with the side surface of the lower electrode layer 53 to conduct electricity.
【００２７】〈実施例３〉本発明のさらに他の実施例で
あるセルの構造断面図を図６に示す。これは上部電極層
とホトマスク数を減らして製造工程を簡略することを目
的としたものでセルの分割は実施例１で述べた主旨と同
じである。図５とほとんどが同じであるが異なる点だけ
を述べると高誘電体層６４の上には上部電極層を成膜せ
ず、高誘電体層６４と直接接触する配線層６８が上部電
極を兼ねる構成である。<Embodiment 3> FIG. 6 is a sectional view showing the structure of a cell according to still another embodiment of the present invention. This is for the purpose of simplifying the manufacturing process by reducing the number of upper electrode layers and photomasks, and the cell division is the same as the purpose described in the first embodiment. 5 except that the upper electrode layer is not formed on the high dielectric layer 64, and the wiring layer 68 directly in contact with the high dielectric layer 64 also serves as the upper electrode. Configuration.
【００２８】〈実施例４〉本発明のさらに他の実施例で
あるセルの構造断面図を図７に示す。これは実施例３で
述べたセルを更に簡略化した構造で図６とほとんどが同
じであるが異なる点だけを述べるとＢＳＴの高誘電体層
４４を外部環境から保護する目的のＳｉＮ膜とＳｉＯ2
膜からなる保護膜が配線層の絶縁膜７６と兼ねているこ
とである。<Embodiment 4> FIG. 7 is a sectional view showing the structure of a cell according to still another embodiment of the present invention. This is a further simplified structure of the cell described in the third embodiment, which is almost the same as FIG. 6 except for the difference. Only the difference is that the SiN film and the SiON film for protecting the high dielectric layer 44 of BST from the external environment are described. Two
That is, the protective film made of the film also serves as the insulating film 76 of the wiring layer.
【００２９】〈実施例５〉本発明の一実施例であるＳｉ
単結晶基板１上に作ったＭＩＭ型薄型コンデンサの製造
方法を図１と図４を参照して説明する。図１（ａ）に示
すように、約５００μｍの厚さのＳｉ単結晶基板１上に
ＳｉＯ2層２を約５００ｎｍの厚みに形成し、これに重
ねてＴｉ−Ｐｔの順番で下部電極層３をスパッタにより
成膜する。Ｔｉの替わりにＴａ等の高融点金属でもよ
く、この厚さは約１００ｎｍである。続いてゾルゲル状
のＢＳＴを溶液とし、この溶液を回転塗布し、約６００
℃の温度の酸素雰囲気中で焼成し、高誘電体層４を約３
００ｎｍの厚さに形成する。高誘電体層４はＢＳＴに限
定されるものではなく、例えばＳＴＯ（ＳｒＴｉ
Ｏ3）、ＰＺＴ（Ｐｂ、ＺｒＴｉＯ3）等の材料でよく、
形成法はスパッタ又はＣＶＤ（化学気相成長法）であっ
てもよい。続いてＴｉ−Ｐｔ−Ａｕの順番に上部電極層
５を形成する。この金属材もこれに限定されるものでは
ない。<Embodiment 5> Si as an embodiment of the present invention
A method for manufacturing a MIM type thin capacitor formed on a single crystal substrate 1 will be described with reference to FIGS. As shown in FIG. 1A, a SiO 2 layer 2 is formed to a thickness of about 500 nm on a Si single crystal substrate 1 having a thickness of about 500 μm, and a lower electrode layer 3 is formed on the SiO 2 layer 2 in the order of Ti—Pt. Is formed by sputtering. A high melting point metal such as Ta may be used instead of Ti, and its thickness is about 100 nm. Subsequently, a sol-gel-like BST was prepared as a solution, and this solution was spin-coated, and was applied for about 600
Sintering in an oxygen atmosphere at a temperature of about 3.degree.
It is formed to a thickness of 00 nm. The high dielectric layer 4 is not limited to BST, for example, STO (SrTi
O 3 ), PZT (Pb, ZrTiO 3 ), etc.
The formation method may be sputtering or CVD (chemical vapor deposition). Subsequently, the upper electrode layer 5 is formed in the order of Ti-Pt-Au. This metal material is not limited to this.
【００３０】ウエーハ全面にＭＩＭ型構造を形成した
後、薄型コンデンサ用に設計されたパターンに対応した
ホトレジスト層を形成し、これをマスクにイオンミリン
グによって上部電極層４５を加工し、順次同じ手法で高
誘電体層４４、下部電極層４３を加工し、分割する。こ
の工程でＭＩＭ型コンデンサは分割位置６で単位セル８
に分割されている。After the MIM type structure is formed on the entire surface of the wafer, a photoresist layer corresponding to the pattern designed for the thin capacitor is formed, and the upper electrode layer 45 is processed by ion milling using the photoresist layer as a mask. The high dielectric layer 44 and the lower electrode layer 43 are processed and divided. In this step, the MIM type capacitor is placed in the unit cell 8 at the dividing position 6.
Is divided into
【００３１】続いて図４に示すように、この表面にＳｉ
Ｏ2絶縁膜４６を形成し、上部電極層４５と下部電極層
４３に達する導通孔を加工し、Ｔｉ−Ｐｔ−Ａｕの順番
で成膜した配線金属を形成し、ホトレジスト層をマスク
にイオンミリングによって配線層４７、４８を加工す
る。これによって下部電極用の配線層４７と上部電極用
の配線層４８によってＭＩＭ型コンデンサの単位セルが
並列に接続され全体で大容量のコンデンサとなる。Subsequently, as shown in FIG.
An O 2 insulating film 46 is formed, a conduction hole reaching the upper electrode layer 45 and the lower electrode layer 43 is processed, a wiring metal formed in the order of Ti—Pt—Au is formed, and ion milling is performed using the photoresist layer as a mask. The wiring layers 47 and 48 are processed by this. As a result, the unit cells of the MIM type capacitor are connected in parallel by the wiring layer 47 for the lower electrode and the wiring layer 48 for the upper electrode, so that the capacitor as a whole has a large capacity.
【００３２】続いてこの表面にＳｉＮ膜とＳｉＯ2膜を
順番にそれぞれ１００ｎｍと６００ｎｍの厚さで成膜し
て保護膜４９とし、これに外部取り出し用の窓を開け表
面側の工程が完了する。上記ＳｉＮ膜は高誘電体層４４
を外部環境から保護する目的で使われるもので、同様の
効果があるＡｌＮ又はＡｌ2Ｏ3であってもよい。Subsequently, a SiN film and a SiO 2 film are sequentially formed on this surface with a thickness of 100 nm and 600 nm, respectively, to form a protective film 49, a window for taking out the outside is opened, and the process on the front side is completed. . The SiN film is a high dielectric layer 44
AlN or Al 2 O 3 which has the same effect and may be used for the purpose of protecting the AlN from the external environment.
【００３３】続いて図１（ｂ）に示すように、約５００
μｍの厚さのＳｉ単結晶基板１の裏面側から約１８０μ
ｍまでＳｉを研削除去し、ＨＦとＨＮＯ3を主成分とし
た化学エッチング液によってＳｉを溶解し、約５０μｍ
の基板厚さにする。この研削でＳｉ単結晶内に生じた損
傷は約５０μｍ以上の量の化学エッチングで完全に除去
できる。これによって約５０μｍの厚さのＳｉ単結晶ウ
エーハ基板上にＭＩＭ型薄型コンデンサが製造され、ウ
エーハの反りは２０μｍ以内になった。なお、図１
（ｂ）は図１（ａ）に対応する部分のみを示したもの
で、実際の素子は図４に示した状態である。この後、ウ
エーハからチップを切り出し、特性の揃ったＭＩＭ型薄
型コンデンサを大量に生産することができた。Subsequently, as shown in FIG.
about 180 μm from the back side of the Si single crystal substrate 1 having a thickness of μm.
m, and the Si was dissolved by a chemical etching solution containing HF and HNO 3 as main components, and about 50 μm
Substrate thickness. Damage caused in the Si single crystal by this grinding can be completely removed by chemical etching of about 50 μm or more. As a result, an MIM type thin capacitor was manufactured on a Si single crystal wafer substrate having a thickness of about 50 μm, and the warpage of the wafer was within 20 μm. FIG.
(B) shows only a portion corresponding to FIG. 1 (a), and the actual element is in the state shown in FIG. Thereafter, chips were cut out from the wafer, and mass-produced MIM type thin capacitors having uniform characteristics were able to be produced.
【００３４】〈実施例６〉図９は薄型ＬＳＩチップ９１
と上記実施例で形成された薄型コンデンサチップ９２を
Ｆカードに実装した主要部分の構成を示す断面構造図で
ある。約２０μｍの薄型ＬＳＩチップ９１と同じ厚さの
薄型コンデンサチップ９２の各々の電極が配線層９８に
導電性樹脂９９によって接続され、これらの周囲の空間
を樹脂９０で充填し、さらに２０μｍ厚のスペーサ９５
及び接着層９４、９６で囲んで同じ厚さの上層と下層の
樹脂フィルム９３、９６（約１００μｍの厚さ）で挟み
固定する。このＦカードの厚さは約２５０μｍと薄いに
も係わらず薄型ＬＳＩチップ９１と薄型コンデンサチッ
プ９２は図のようにＦカードの厚み方向の中央（中立
面）に配置されるので、カードの曲げやねじれに対する
強度は図８の従来ＩＣカード（約７５０μｍ厚）に比べ
一桁以上大きくなっている。Embodiment 6 FIG. 9 shows a thin LSI chip 91.
FIG. 3 is a cross-sectional structural view showing a configuration of a main part in which the thin capacitor chip 92 formed in the above embodiment is mounted on an F card. Each electrode of the thin capacitor chip 92 having the same thickness as the thin LSI chip 91 having a thickness of about 20 μm is connected to the wiring layer 98 by a conductive resin 99, the space around these is filled with the resin 90, and a spacer having a thickness of 20 μm is further provided. 95
And, it is sandwiched and fixed between the upper and lower resin films 93 and 96 (thickness of about 100 μm) of the same thickness surrounded by the adhesive layers 94 and 96. Although the thickness of the F card is as thin as about 250 μm, the thin LSI chip 91 and the thin capacitor chip 92 are arranged at the center (neutral surface) in the thickness direction of the F card as shown in the figure, so that the card is bent. The strength against twisting and twisting is at least one digit greater than that of the conventional IC card (about 750 μm thick) in FIG.
【００３５】図１０は非接触方式ＩＣカードであるＦカ
ード１００の全体構成図である。Ｆカード１００は同調
用コイル１０１と薄型ＬＳＩチップ９１、９１’と薄型
コンデンサチップ９２と配線層９８を有する。図１１は
この電気回路系統図である。薄型コンデンサチップはＬ
Ｃｍ同調回路と全波整流の平滑用コンデンサＣｐに使わ
れ、Ｆカードの特徴である効果を確認した。FIG. 10 is an overall configuration diagram of an F card 100 which is a non-contact type IC card. The F card 100 includes a tuning coil 101, thin LSI chips 91 and 91 ', a thin capacitor chip 92, and a wiring layer 98. FIG. 11 is an electric circuit diagram. The thin capacitor chip is L
It was used for the Cm tuning circuit and the smoothing capacitor Cp for full-wave rectification, and confirmed the effects characteristic of the F card.
【００３６】なお、薄型コンデンサの用途はＦカードに
限定されるものではなく、厚さの薄い特徴を生かして、
携帯端末機器等の小型軽量の目的のためにマルチチップ
モジュール実装に適用される。さらに例えばＤＲＡＭ等
の大型ＬＳＩの表面にこれを接着、接続して電源雑音を
低減する等の新しい応用分野が開拓できる。また、本発
明では薄型コンデンサチップの例を述べたが、同様の原
理でこれを薄型ＬＳＩチップ内にも適用できることは云
うに及ばない。The use of the thin capacitor is not limited to the F card, and the thin capacitor is used to
It is applied to the mounting of a multi-chip module for the purpose of miniaturization and light weight of a portable terminal device or the like. Further, a new application field such as reducing the power supply noise by bonding and connecting this to the surface of a large LSI such as a DRAM can be developed. In the present invention, an example of a thin capacitor chip has been described, but it goes without saying that the same principle can be applied to a thin LSI chip.
【００３７】[0037]
【発明の効果】以上述べたように、本発明の半導体装置
は、製造歩留まりが従来より向上し、大量生産に適し、
取り扱いやすく、また、組立歩留まりも良好であった。
また、このような半導体装置を容易に製造することがで
きた。また、曲げやねじりに対して強靭なフレキシブル
カードとすることができた。As described above, according to the semiconductor device of the present invention, the production yield is improved as compared with the conventional one, and it is suitable for mass production.
It was easy to handle and the assembly yield was good.
Further, such a semiconductor device could be easily manufactured. In addition, a flexible card that is strong against bending and torsion could be obtained.
【図１】本発明の半導体装置の一例の断面構造図。FIG. 1 is a sectional structural view of an example of a semiconductor device of the present invention.
【図２】本発明の実施例１の半導体装置の平面図。FIG. 2 is a plan view of the semiconductor device according to the first embodiment of the present invention.
【図３】本発明の実施例１の半導体装置の断面構造図。FIG. 3 is a sectional structural view of the semiconductor device according to the first embodiment of the present invention;
【図４】本発明の実施例１の半導体装置の単位セルの断
面構造図。FIG. 4 is a sectional structural view of a unit cell of the semiconductor device according to the first embodiment of the present invention.
【図５】本発明の実施例２の半導体装置の単位セルの断
面構造図。FIG. 5 is a sectional structural view of a unit cell of a semiconductor device according to a second embodiment of the present invention.
【図６】本発明の実施例３の半導体装置の単位セルの断
面構造図。FIG. 6 is a sectional structural view of a unit cell of a semiconductor device according to a third embodiment of the present invention.
【図７】本発明の実施例４の半導体装置の単位セルの断
面構造図。FIG. 7 is a sectional structural view of a unit cell of a semiconductor device according to a fourth embodiment of the present invention.
【図８】従来のＩＣカードの主要部分の構成を示す断面
構造図。FIG. 8 is a sectional structural view showing a configuration of a main part of a conventional IC card.
【図９】本発明の実施例６に示したＦカードの主要部分
の構成を示す断面構造図。FIG. 9 is a sectional structural view showing a configuration of a main part of an F card shown in Embodiment 6 of the present invention.
【図１０】本発明の実施例６に示したＦカードの全体構
成図。FIG. 10 is an overall configuration diagram of an F card shown in Embodiment 6 of the present invention.
【図１１】本発明の実施例６に示したＦカードの電気回
路系統図。FIG. 11 is an electric circuit diagram of an F card according to a sixth embodiment of the present invention.
１…Ｓｉ単結晶基板 ２…ＳｉＯ2層 ３、４３、５３、６３、７３…下部電極層 ４、４４、５４、６４、７４…高誘電体層 ５、４５、５５…上部電極層 ６…分割位置 ８…単位セル ２０…チップ ２１…コンデンサ部 ２６…セル ２９…スクライプ領域 ４６、５６、６６、７６…ＳｉＯ2絶縁膜 ４７、４８、５７、５８、６７、６８、７７、７８、９
８…配線層 ４９、５９…保護膜層 ７６…絶縁膜 ８１…ＬＳＩチップ ８２…コンデンサチップ ８３、８７、９３、９６…樹脂フィルム ８４、８６、９４、９６…接着層 ８５…コア層 ８８…ワイヤ ９１、９１’…薄型ＬＳＩチップ ９２…薄型コンデンサチップ ９５…スペーサ ９９…導電性樹脂 １００…Ｆカード １０１…同調用コイル1 ... Si single crystal substrate 2 ... SiO 2 layer 3,43,53,63,73 ... lower electrode layer 4,44,54,64,74 ... high dielectric layer 5,45,55 ... upper electrode layer 6 ... divided position 8 ... unit cell 20 ... chip 21 ... condenser 26 ... cell 29 ... Sukuraipu regions 46, 56, 66 and 76 ... SiO 2 insulating film 47,48,57,58,67,68,77,78,9
8 Wiring layer 49, 59 Protective film layer 76 Insulating film 81 LSI chip 82 Capacitor chip 83, 87, 93, 96 Resin film 84, 86, 94, 96 Adhesive layer 85 Core layer 88 Wire 91, 91 ': Thin LSI chip 92: Thin capacitor chip 95: Spacer 99: Conductive resin 100: F card 101: Tuning coil
───────────────────────────────────────────────────── フロントページの続き (51)Int.Cl.6 識別記号 庁内整理番号 ＦＩ 技術表示箇所 Ｈ０１Ｌ 25/18 (72)発明者 小田 浩人 東京都小平市上水本町５丁目20番１号 日 立超エル・エス・アイ・エンジニアリング 株式会社内 (72)発明者 太田 博 東京都小平市上水本町５丁目20番１号 日 立超エル・エス・アイ・エンジニアリング 株式会社内 (72)発明者 宇佐美 光雄 東京都国分寺市東恋ケ窪一丁目280番地 株式会社日立製作所中央研究所内──────────────────────────────────────────────────続 き Continuation of the front page (51) Int.Cl. 6 Identification code Agency reference number FI Technical display location H01L 25/18 (72) Inventor Hiroto Oda 5-2-1, Kamimizuhoncho, Kodaira-shi, Tokyo (72) Inventor Hiroshi Ota 5-20-1, Josuihoncho, Kodaira-shi, Tokyo In-house Hitachi, Ltd. (72) Invention Mitsuo Usami 1-280 Higashi Koigakubo, Kokubunji-shi, Tokyo Inside the Central Research Laboratory, Hitachi, Ltd.
Claims (10)
半導体基板と該半導体基板に配置された素子からなる半
導体装置であり、該素子を構成する成膜層の内の少なく
とも一層が分割され、分割された各素子は、並列に接続
されたことを特徴とする半導体装置。1. A semiconductor device comprising a semiconductor substrate having a thickness in a range of 1 μm to 100 μm and an element arranged on the semiconductor substrate, wherein at least one of film formation layers constituting the element is divided, A semiconductor device, wherein each of the divided elements is connected in parallel.
のコンデンサであることを特徴とする請求項１記載の半
導体装置。2. The semiconductor device according to claim 1, wherein said element is a capacitor having a metal-insulator-metal structure.
成膜層の内の最も応力が大きい層であることを特徴とす
る請求項１又は２記載の半導体装置。3. The semiconductor device according to claim 1, wherein the divided layer is a layer having the largest stress among the film forming layers constituting the element.
い層は、縦、横いずれも一辺の長さが上記半導体基板の
厚さの１倍から２０倍の範囲であることを特徴とする請
求項１から３のいずれか一に記載の半導体装置。4. The largest planar layer among the divided layers has a length of one side both in the vertical and horizontal directions in a range of 1 to 20 times the thickness of the semiconductor substrate. The semiconductor device according to claim 1, wherein:
あることを特徴とする請求項１から４のいずれか一に記
載の半導体装置。5. The semiconductor device according to claim 1, wherein said semiconductor substrate is a silicon single crystal substrate.
を形成する工程、該素子を構成する成膜層の内の少なく
とも一層を分割する工程、分割された各素子を並列に接
続するための配線層の少なくとも一部を形成する工程及
び上記半導体基板の裏面を研磨し、その厚さを１μｍか
ら１００μｍ範囲の厚さとする工程を有することを特徴
とする半導体装置の製造方法。6. A step of forming an element composed of a plurality of film layers on a semiconductor substrate, a step of dividing at least one of the film layers constituting the element, and connecting the divided elements in parallel. Forming at least a part of a wiring layer for the semiconductor device, and polishing the back surface of the semiconductor substrate to reduce the thickness thereof to a thickness in a range of 1 μm to 100 μm.
磨を行って後に化学的研磨を行うことを特徴とする請求
項６記載の半導体装置の製造方法。7. The method of manufacturing a semiconductor device according to claim 6, wherein the polishing of the back surface of the semiconductor substrate is performed by performing mechanical polishing and then performing chemical polishing.
のコンデンサであることを特徴とする請求項６又は７記
載の半導体装置の製造方法。8. The method according to claim 6, wherein the element is a capacitor having a metal-insulator-metal structure.
体装置と、該半導体装置を内部に配置したフレキシブル
な構造材からなることを特徴とするフレキシブルカー
ド。9. A flexible card comprising: the semiconductor device according to claim 1; and a flexible structural member having the semiconductor device disposed therein.
ードであることを特徴とする請求項９記載のフレキシブ
ルカード。10. The flexible card according to claim 9, wherein said flexible card is a contactless card.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP23501696A JPH1079471A (en) | 1996-09-05 | 1996-09-05 | Semiconductor device, its manufacture and flexible card |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP23501696A JPH1079471A (en) | 1996-09-05 | 1996-09-05 | Semiconductor device, its manufacture and flexible card |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH1079471A true JPH1079471A (en) | 1998-03-24 |
Family
ID=16979834
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP23501696A Pending JPH1079471A (en) | 1996-09-05 | 1996-09-05 | Semiconductor device, its manufacture and flexible card |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH1079471A (en) |
Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6319765B1 (en) | 1998-12-30 | 2001-11-20 | Hyundai Electronics Industries Co., Ltd. | Method for fabricating a memory device with a high dielectric capacitor |
| JP2005159259A (en) * | 2003-10-31 | 2005-06-16 | Univ Waseda | Thin-film capacitor, high-density mounting board with built-in thin-film capacitor, and method of manufacturing thin-film capacitor |
| WO2005093647A1 (en) * | 2004-03-26 | 2005-10-06 | Semiconductor Energy Laboratory Co., Ltd. | Thin semiconductor device and operation method of thin semiconductor device |
| JP2007528601A (en) * | 2004-03-09 | 2007-10-11 | インフィネオン テクノロジーズ アクチエンゲゼルシャフト | Reliable, cost effective and thermally strong AuSn die attach technology |
| JP2008072149A (en) * | 2007-12-03 | 2008-03-27 | Kansai Electric Power Co Inc:The | Semiconductor device |
| JP2008271283A (en) * | 2007-04-23 | 2008-11-06 | Audio Technica Corp | Condenser microphone |
-
1996
- 1996-09-05 JP JP23501696A patent/JPH1079471A/en active Pending
Cited By (10)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6319765B1 (en) | 1998-12-30 | 2001-11-20 | Hyundai Electronics Industries Co., Ltd. | Method for fabricating a memory device with a high dielectric capacitor |
| JP2005159259A (en) * | 2003-10-31 | 2005-06-16 | Univ Waseda | Thin-film capacitor, high-density mounting board with built-in thin-film capacitor, and method of manufacturing thin-film capacitor |
| JP4523299B2 (en) * | 2003-10-31 | 2010-08-11 | 学校法人早稲田大学 | Thin film capacitor manufacturing method |
| US7836567B2 (en) | 2003-10-31 | 2010-11-23 | Waseda University | Thin film capacitor, high-density packaging substrate incorporating thin film capacitor, and method for manufacturing thin-film capacitor |
| JP2007528601A (en) * | 2004-03-09 | 2007-10-11 | インフィネオン テクノロジーズ アクチエンゲゼルシャフト | Reliable, cost effective and thermally strong AuSn die attach technology |
| JP4700681B2 (en) * | 2004-03-09 | 2011-06-15 | インフィネオン テクノロジーズ アクチエンゲゼルシャフト | Si circuit die, method of manufacturing Si circuit die, method of attaching Si circuit die to heat sink, circuit package and power module |
| WO2005093647A1 (en) * | 2004-03-26 | 2005-10-06 | Semiconductor Energy Laboratory Co., Ltd. | Thin semiconductor device and operation method of thin semiconductor device |
| US9030298B2 (en) | 2004-03-26 | 2015-05-12 | Semiconductor Energy Laboratory Co., Ltd. | Thin semiconductor device and operation method of thin semiconductor device |
| JP2008271283A (en) * | 2007-04-23 | 2008-11-06 | Audio Technica Corp | Condenser microphone |
| JP2008072149A (en) * | 2007-12-03 | 2008-03-27 | Kansai Electric Power Co Inc:The | Semiconductor device |
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