JPH10308473A - Manufacture for semiconductor package - Google Patents

Manufacture for semiconductor package

Info

Publication number
JPH10308473A
JPH10308473A JP9119220A JP11922097A JPH10308473A JP H10308473 A JPH10308473 A JP H10308473A JP 9119220 A JP9119220 A JP 9119220A JP 11922097 A JP11922097 A JP 11922097A JP H10308473 A JPH10308473 A JP H10308473A
Authority
JP
Japan
Prior art keywords
semiconductor package
fixing
resin
manufacturing
electrode
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP9119220A
Other languages
Japanese (ja)
Other versions
JP4115553B2 (en
Inventor
Yoshihiro Ishida
芳弘 石田
Kiyoshi Shimizu
潔 清水
Tetsuo Sato
哲夫 佐藤
Shinichi Nishikata
進一 西方
Atsushi Komura
敦 小村
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Citizen Watch Co Ltd
Original Assignee
Citizen Watch Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority to JP11922097A priority Critical patent/JP4115553B2/en
Application filed by Citizen Watch Co Ltd filed Critical Citizen Watch Co Ltd
Priority to EP98917679.7A priority patent/EP0932198B1/en
Priority to CNB988005794A priority patent/CN1185702C/en
Priority to EP08167595.1A priority patent/EP2015359B1/en
Priority to PCT/JP1998/001905 priority patent/WO1998052220A1/en
Priority to KR1019997000071A priority patent/KR100568571B1/en
Priority to US09/194,735 priority patent/US6365438B1/en
Priority to TW087106959A priority patent/TW395033B/en
Priority to MYPI98002064A priority patent/MY123937A/en
Publication of JPH10308473A publication Critical patent/JPH10308473A/en
Application granted granted Critical
Publication of JP4115553B2 publication Critical patent/JP4115553B2/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/93—Batch processes
    • H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L24/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/93—Batch processes
    • H01L2224/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L2224/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01004—Beryllium [Be]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01005—Boron [B]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01006—Carbon [C]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01019—Potassium [K]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01029—Copper [Cu]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01033—Arsenic [As]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01039—Yttrium [Y]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01078—Platinum [Pt]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01079—Gold [Au]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Dicing (AREA)

Abstract

PROBLEM TO BE SOLVED: To provide a manufacture for an inexpensive, highly reliable semiconductor package which is mounted on a small-sized portable unit and is manufactured with improved productivity. SOLUTION: A plurality of wiring patterns for mounting an IC chip and electrode patterns for forming electrodes to be joined to the outside are arranged on an integrated circuit board 1A. Next, an IC chip 6 is mounted on the wiring pattern and is sealed with sealing resin 7. Next, a bump ball electrode 9 to be joined to the outside is formed. This makes an integrated package and fixes the ball electrode 9 of the integrated package to a base member 8. Then the held integrated package is cut along a cut line 2 to form an individual complete semiconductor package. This is the most suitable manufacture for a chip size/ scale package and is superior in reliability and productivity.

Description

【発明の詳細な説明】DETAILED DESCRIPTION OF THE INVENTION

【０００１】[0001]

【発明の属する技術分野】本発明は半導体パッケージの
製造方法に係わり、更に詳しくは外部接続用の突起電極
を有する半導体パッケージの製造方法に関するものであ
る。The present invention relates to a method of manufacturing a semiconductor package, and more particularly to a method of manufacturing a semiconductor package having a projection electrode for external connection.

【０００２】[0002]

【従来の技術】近年、半導体パッケージの小型化、高密
度化に伴いベア・チップを直接フェイスダウンで、基板
上に実装するフリップチップボンディングが開発されて
いる。カメラ一体型ＶＴＲや携帯電話機等の登場によ
り、ベア・チップと略同じ寸法の小型パッケージ、所謂
ＣＳＰ（チップサイズ／スケール・パッケージ）を載せ
た携帯機器が相次いで登場してきている。最近ＣＳＰの
開発は急速に進み、その市場要求が本格化している。2. Description of the Related Art In recent years, with the miniaturization and high density of semiconductor packages, flip chip bonding has been developed in which bare chips are directly mounted face down on a substrate. With the advent of camera-integrated VTRs and mobile phones, portable devices equipped with a small package having substantially the same dimensions as a bare chip, that is, a so-called CSP (chip size / scale package) are appearing one after another. Recently, CSP development has progressed rapidly, and the market demand has been in full swing.

【０００３】図６は、多数個取りし、高密度実装化した
従来技術が特開平８−１５３８１９号公報に開示されて
いる。以下図面に基づいてその概要を説明する。FIG. 6 shows a prior art in which a large number of pieces are taken and high-density mounting is carried out in JP-A-8-153819. The outline will be described below with reference to the drawings.

【０００４】図６において、短冊状の回路基板１にスル
ーホール２を形成後、銅メッキ層を施す工程と、全ての
回路パターンと接続する共通電極１４を含む複数個、例
えば２個のＢＧＡを構成する回路パターンを形成する回
路パターン形成工程と、前記回路基板１の上下両面に感
光性樹脂皮膜を施した後、エッチングにより、共通電極
１４及びＩＣチップ、ボンディングワイヤ、半田バンプ
の各接続部を除くようにドライフイルムを形成するドラ
イフイルムラミネート工程と、前記共通電極１４を利用
して前記回路基板１の上下両面の露出している電極の銅
メッキ層の表面に、Ｎｉ−Ａｕメッキ層を形成する。In FIG. 6, after a through hole 2 is formed in a strip-shaped circuit board 1, a copper plating layer is applied, and a plurality of, for example, two BGAs including a common electrode 14 connected to all circuit patterns are formed. A circuit pattern forming step of forming a circuit pattern to be formed, and after applying a photosensitive resin film on the upper and lower surfaces of the circuit board 1, the common electrode 14 and the respective connection portions of the IC chip, bonding wires, and solder bumps are etched. A dry film laminating step of forming a dry film so as to remove, and forming a Ni—Au plating layer on the surfaces of the copper plating layers of the exposed electrodes on the upper and lower surfaces of the circuit board 1 using the common electrode 14. I do.

【０００５】次に、共通電極１４と回路パターンとを分
離するパターン分離工程は、製品分離ライン１５の四辺
に沿って、その四隅に回路基板１と連結する連結部１５
ａを残すように、ルータ加工により長穴１６を穴明けす
る。その後、ワイヤーボンディング及びトランスファー
モールドにより樹脂封止し、回路基板１の下面に半田バ
ンプを形成する。Next, a pattern separating step for separating the common electrode 14 from the circuit pattern is performed along four sides of the product separation line 15 at the four corners of the connecting portion 15 for connecting to the circuit board 1.
A long hole 16 is made by router processing so as to leave a. Thereafter, resin sealing is performed by wire bonding and transfer molding, and solder bumps are formed on the lower surface of the circuit board 1.

【０００６】製品分離工程は、前記四隅に残した連結部
は狭隘なため、プレス抜き等の切り離し手段で余分な負
荷をかけることなく極めて容易に分離することにより、
単個のＢＧＡを製造することができる。[0006] In the product separation step, since the connection portions left at the four corners are narrow, separation can be performed very easily by a separation means such as a press without applying an extra load.
A single BGA can be manufactured.

【０００７】しかしながら、前述した短冊状の複数個取
りする半導体パッケージの製造方法は、単個の半導体パ
ッケージの製造方法に比較して生産性は若干向上する
が、小型パッケージであるＣＳＰにおいては、回路基板
製造時の基板取り個数が少なく、生産コストが高くな
る。また、前記ＣＳＰのように、前記回路基板の外縁か
ら最外周に位置するボール電極の中心までの距離が差が
無くなると、製品分離工程でプレス抜き等の切り離し手
段で分離する時の金型押さえ代が無くなる等の問題があ
った。However, the above-described method of manufacturing a semiconductor package in which a plurality of strip-shaped semiconductor packages are obtained has a slight improvement in productivity as compared with the method of manufacturing a single semiconductor package. The number of substrates to be manufactured at the time of substrate manufacture is small, and the production cost is increased. Further, when the distance from the outer edge of the circuit board to the center of the ball electrode located at the outermost periphery is eliminated as in the case of the CSP, when the mold is separated by a separation means such as a press punch in a product separation process, the die is pressed. There was a problem that the bill was lost.

【０００８】そこで、小型携帯機器等に搭載するＣＳＰ
の従来の半導体パッケージの製造方法について以下その
概要を説明する。Therefore, a CSP mounted on a small portable device or the like
An outline of the conventional semiconductor package manufacturing method will be described below.

【０００９】先ず図７（ａ）に示す多数個取りする回路
基板形成工程は、両面銅張りされた集合回路基板１Ａに
スルーホール（図示しない）を形成した後、無電解銅メ
ッキ及び電解銅メッキにより銅メッキ層を形成し、更に
メッキレジストをラミネートし、露光現像してパターン
マスクを形成した後、エッチング液を用いてパターンエ
ッチングを行うことにより、前記集合回路基板１Ａの上
面側には複数個分配列したＩＣ接続用電極３、下面側に
パッド電極である外部接続用電極４を形成する。次にソ
ルダーレジスト処理を行い、所定の部分にレジスト膜を
形成することにより、前記集合回路基板１Ａの下面側に
は外部接続用電極４を露呈するように、マトリックス状
に多数の同一形状の半田付け可能な表面であるレジスト
膜の開口部を形成し、多数個取りする集合回路基板１Ａ
が完成される。２はＸ、Ｙ方向に直交するカットライン
である。First, in the circuit board forming step shown in FIG. 7 (a), a through hole (not shown) is formed in a collective circuit board 1A having copper clad on both sides, and then electroless copper plating and electrolytic copper plating are performed. After forming a copper plating layer, further laminating a plating resist, exposing and developing to form a pattern mask, and performing pattern etching using an etchant, a plurality of patterns are formed on the upper surface side of the collective circuit board 1A. IC connection electrodes 3 arranged separately and external connection electrodes 4 as pad electrodes are formed on the lower surface side. Next, a solder resist process is performed to form a resist film on a predetermined portion, so that a large number of solders of the same shape are formed in a matrix so as to expose the external connection electrodes 4 on the lower surface side of the integrated circuit board 1A. Collective circuit board 1A in which openings of a resist film, which is a surface that can be attached, are formed and a large number of pieces are formed.
Is completed. 2 is a cut line orthogonal to the X and Y directions.

【００１０】図７（ｂ）に示すＩＣチップ実装工程は、
先ず、ＩＣウエハーをバンプ工程に流して前記ＩＣウエ
ハーのパッド電極面に半田バンプ５を形成する。前記半
田バンプ５の形成方法には、一般に、スタッドバンプ方
式、ボールバンプ方式、及びメッキバンプ方式等がある
が、その中で、パッド電極位置にレジストにて窓を形成
し半田浴槽中に浸漬してメッキにて半田バンプを形成す
るメッキバンプ方式は、パッド電極間の狭い配列でバン
プを形成することが可能で、ＩＣチップの小型化には有
効な半田バンプの形成手段である。The IC chip mounting process shown in FIG.
First, a solder bump 5 is formed on a pad electrode surface of the IC wafer by flowing the IC wafer to a bump process. The method for forming the solder bump 5 is generally a stud bump method, a ball bump method, a plating bump method, etc. Among them, a window is formed with a resist at a pad electrode position, and immersed in a solder bath. The plating bump method of forming solder bumps by plating can form bumps in a narrow arrangement between pad electrodes, and is an effective means of forming solder bumps for miniaturizing IC chips.

【００１１】前記半田バンプ５を形成後、前記ＩＣウエ
ハーを粘着テープ等で貼着した状態で、所定のチップサ
イズにダイシングソー等の装置でウエハーの厚みをフル
カット方式でＸ、Ｙ方向に切断した後、ＩＣチップ６を
単体に分割する。After the solder bumps 5 are formed, the thickness of the wafer is cut in the X and Y directions by a full-cut method using a device such as a dicing saw in a state where the IC wafer is adhered with an adhesive tape or the like. After that, the IC chip 6 is divided into single pieces.

【００１２】前記半田バンプ付きＩＣチップ６、又は前
述した集合回路基板１Ａの前記配線バターンの所定位置
にフラックスを塗布して、単体に分割した前記ＩＣチッ
プ６を１個づつ複数個分配列した集合回路基板１Ａの個
々の回路基板１上の所定位置に搭載した後、半田リフロ
ー工程を経て、フリップチップ実装を行う。A flux is applied to a predetermined position of the wiring pattern of the IC chip 6 with solder bumps or the wiring pattern of the above-mentioned collective circuit board 1A, and a plurality of the IC chips 6 divided into single pieces are arranged one by one. After being mounted at a predetermined position on each circuit board 1 of the circuit board 1A, flip-chip mounting is performed through a solder reflow process.

【００１３】図７（ｃ）に示す封止工程は、熱硬化性の
封止樹脂７で前記隣接する複数個のＩＣチップ５に跨が
った状態で、サイドポッティングにより一体的に樹脂封
止することにより、ＩＣチップ６はフェイスダウンで集
合回路基板１Ａの個々の回路基板１上に固定される。In the sealing step shown in FIG. 7C, the resin is integrally sealed by side potting with the thermosetting sealing resin 7 straddling the plurality of IC chips 5 adjacent to each other. By doing so, the IC chip 6 is fixed face down on the individual circuit boards 1 of the collective circuit board 1A.

【００１４】図８（ａ）に示す基準部材張り付け工程
は、ＩＣチップ６を実装した集合回路基板１Ａの平坦な
底面を、基準部材８上に接着剤又は粘着テープ等の固定
手段で張り付ける。張り付け面が互いに平坦なため、確
実に固定される。In the reference member attaching step shown in FIG. 8A, the flat bottom surface of the collective circuit board 1A on which the IC chip 6 is mounted is attached to the reference member 8 by a fixing means such as an adhesive or an adhesive tape. Since the attachment surfaces are flat to each other, they are securely fixed.

【００１５】図８（ｂ）は、タイシング工程で、前述の
Ｘ、Ｙ方向のカットライン２に沿って、ダイシングソー
等の切削手段で単個に切削、分割した後、溶解液等によ
り基準部材８より剥離する。FIG. 8 (b) shows a tying step, in which the cutting member such as a dicing saw is singly cut and divided along a cutting line 2 in the X and Y directions, and then a reference member is formed with a dissolving liquid or the like. 8 to peel off.

【００１６】図８（ｃ）は、ボール電極を形成するボー
ル形成工程は切削、分離された個々の回路基板１の下面
側に形成された外部接続用電極４の位置に、半田ボール
を配置してリフローすることによりボール電極９を形成
する。以上の工程により単個のフリップチップＢＧＡ２
０が完成される。FIG. 8C shows that the ball forming step for forming the ball electrodes is such that solder balls are arranged at the positions of the external connection electrodes 4 formed on the lower surface side of each of the circuit boards 1 cut and separated. The ball electrode 9 is formed by reflow. Through the above steps, a single flip chip BGA2
0 is completed.

【００１７】[0017]

【発明が解決しようとする課題】しかしながら、前述し
た半導体パッケージの製造方法には次のような問題点が
ある。即ち、半田ボール付けは、単個に切削、分割され
た回路基板毎に半田ボークを配置して行うもので、小型
パッケージであるＣＳＰにおいては、回路基板１の外縁
から最外周に位置するボール電極の中心までの距離が無
くなると、半田ボール付け時の治具スペースが取れなく
なる。また、個々に半田ボール付けを行うので生産性が
低く、コストアップ等の問題があった。However, the above-described method for manufacturing a semiconductor package has the following problems. That is, soldering is performed by arranging solder balls on each of a single cut and divided circuit board, and in a CSP which is a small package, a ball electrode located at the outermost periphery from the outer edge of the circuit board 1 When the distance to the center of the solder ball is lost, the jig space at the time of solder ball attachment cannot be obtained. In addition, since solder balls are individually applied, productivity is low, and there is a problem such as an increase in cost.

【００１８】本発明は、上記従来の課題に鑑みなされた
ものであり、その目的は、小型携帯機器等に搭載する信
頼性及び生産性に優れた、安価な半導体パッケージの製
造方法を提供するものである。The present invention has been made in view of the above-mentioned conventional problems, and has as its object to provide a method of manufacturing an inexpensive semiconductor package which is excellent in reliability and productivity and is mounted on a small portable device or the like. It is.

【００１９】[0019]

【課題を解決するための手段】上記目的を達成するため
に、本発明における半導体パッケージの製造方法は、Ｉ
Ｃチップを実装した半導体パッケージの製造方法におい
て、前記ＩＣチップ実装用のボンディングパターンと外
部接続用電極を形成するための電極パターンとを集合回
路基板面に複数個分配列して形成する回路基板形成工程
と、前記ボンディングパターンと前記ＩＣチップを電気
的接続するＩＣチップ実装工程と、該ＩＣチップを樹脂
封止する封止工程と、前記外部接続用電極に突起電極を
形成する電極形成工程とによりパッケージ集合体を形成
し、該パッケージ集合体の突起電極を基準部材に固定す
る保持工程と、保持されたパッケージ集合体の回路基板
を切削して単個の完成半導体パッケージを形成する切削
工程とからなることを特徴とするものである。In order to achieve the above object, a method of manufacturing a semiconductor package according to the present invention comprises the steps of:
In a method of manufacturing a semiconductor package having a C chip mounted thereon, a circuit board is formed by arranging a plurality of bonding patterns for mounting the IC chip and electrode patterns for forming electrodes for external connection on a surface of a collective circuit board. An IC chip mounting step of electrically connecting the bonding pattern and the IC chip, a sealing step of sealing the IC chip with a resin, and an electrode forming step of forming a protruding electrode on the external connection electrode. Forming a package assembly, a holding step of fixing the projecting electrodes of the package assembly to a reference member, and a cutting step of cutting a circuit board of the held package assembly to form a single completed semiconductor package It is characterized by becoming.

【００２０】また、前記パッケージ集合体保持工程は、
突起電極の端面を平坦化する平坦化工程と、該平坦化さ
れた突起電極を基準部材に固着する固定工程とからなる
ことを特徴とするものである。Further, the package assembly holding step includes:
The method is characterized by comprising a flattening step of flattening an end face of the protruding electrode, and a fixing step of fixing the flattened protruding electrode to a reference member.

【００２１】また、前記平坦化工程は、突起電極の端面
を切削して平坦化することを特徴とするものである。Further, the flattening step is characterized in that the end face of the protruding electrode is cut and flattened.

【００２２】また、前記平坦化工程は、突起電極の端面
を加熱して平坦化することを特徴とするものである。The flattening step is characterized in that the end face of the protruding electrode is flattened by heating.

【００２３】また、前記突起電極を基準部材に固定する
保持工程は、接着剤で固着することを特徴とするもので
ある。Further, the holding step of fixing the protruding electrode to the reference member is characterized by fixing with an adhesive.

【００２４】また、前記パッケージ集合体保持工程は、
突起電極を樹脂で埋没させ、該樹脂により突起電極側に
平坦面を形成する平坦面形成工程と、該平坦面を基準部
材に固着する固定工程とからなることを特徴とするもの
である。Further, the package assembly holding step includes:
The method is characterized by comprising a flat surface forming step of burying the protruding electrode with a resin and forming a flat surface on the protruding electrode side with the resin, and a fixing step of fixing the flat surface to a reference member.

【００２５】また、前記パッケージ集合体保持工程は、
基準部材上に設けられた、温度変化により可逆的に固体
と液体に状態変化する材料内に、液体の状態で突起電極
の端面の一部を埋没し、固体の状態で基準部材上に固着
する固定工程とからなることを特徴とするものである。The package assembly holding step includes:
A part of the end surface of the protruding electrode is buried in a liquid state in a material provided on the reference member and reversibly changed into a solid and a liquid by a temperature change, and is fixed on the reference member in a solid state. And a fixing step.

【００２６】また、前記樹脂による平坦面形成工程は、
スクリーン印刷による樹脂で埋没したことを特徴とする
ものである。Further, the step of forming a flat surface with the resin comprises:
It is characterized by being buried in a resin by screen printing.

【００２７】また、前記樹脂による平坦面形成工程は、
突起電極間に樹脂を樹脂を流し込むことにより、樹脂で
埋没したことを特徴とするものである。The step of forming a flat surface by using the resin includes:
The resin is buried in the resin by pouring the resin between the protruding electrodes.

【００２８】また、前記固定工程は、紫外線反応型樹脂
で固着したことを特徴とするものである。Further, the fixing step is characterized in that the fixing step is performed by using an ultraviolet reactive resin.

【００２９】また、前記固定工程は、熱反応型樹脂で固
着したことを特徴とするものである。Further, the fixing step is characterized by fixing with a heat-reactive resin.

【００３０】また、前記固定工程は、溶剤反応型樹脂で
固着したことを特徴とするものである。Further, the fixing step is characterized by fixing with a solvent type resin.

【００３１】また、前記保持工程は、突起電極の端面を
真空吸着したことを特徴とするものである。In the holding step, the end surface of the protruding electrode is vacuum-adsorbed.

【００３２】また、前記突起電極は、半田バンプである
ことを特徴とするものである。Further, the projecting electrode is a solder bump.

【００３３】また、前記切削工程は、ダイシングソーに
よる切削で行うことを特徴とするものである。Further, the cutting step is performed by cutting with a dicing saw.

【００３４】[0034]

【発明の実施の形態】以下図面に基づいて本発明におけ
る半導体パッケージの製造方法について説明する。図１
及び図２は本発明の実施の形態で、突起電極付きの半導
体パッケージの製造工程を示す説明図である。従来技術
と同一部材は同一符号で示す。DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS A method for manufacturing a semiconductor package according to the present invention will be described below with reference to the drawings. FIG.
FIG. 2 is an explanatory view showing a manufacturing process of a semiconductor package having a bump electrode according to an embodiment of the present invention. The same members as those in the prior art are denoted by the same reference numerals.

【００３５】先ず、図１（ａ）の回路基板形成工程、図
１（ｂ）のＩＣ実装工程、図１（ｃ）の樹脂封止工程
は、前述の従来技術と同様であるので、説明は省略す
る。First, the circuit board forming step of FIG. 1A, the IC mounting step of FIG. 1B, and the resin sealing step of FIG. Omitted.

【００３６】図２（ａ）に示すボール電極を形成するボ
ール付け工程は、前記集合回路基板１Ａの個々の回路基
板１の下面側に形成された外部接続用電極４の位置に、
半田ボールを配置してリフローすることにより突起電極
であるボール電極９が形成される。The ball-attaching step of forming the ball electrodes shown in FIG. 2A is performed at the positions of the external connection electrodes 4 formed on the lower surface side of the individual circuit boards 1 of the collective circuit board 1A.
By arranging and reflowing the solder balls, ball electrodes 9 which are protruding electrodes are formed.

【００３７】図２（ｂ）に示す基準部材張り付け工程
は、後述するボール平坦化工程後に、該ボール端面に形
成した平坦面を基準部材８に接着剤、例えば、日東電工
（株）製の熱剥離テープ「エレップホルダー感圧型ダイ
シングテープ、ＳＰＶ−２２４」等の固定手段により張
りつけるか、後述するボール電極９面を樹脂で埋没させ
て平坦面を形成し、該平坦面を基準部材８に接着剤等の
固定手段により張りつけるか、又は、後述する温度によ
り可逆的に固体と液体に状態変化する材料内にボール電
極９の端面の一部を埋没し、固体状態で基準部材８上に
固定する。更に、ボール電極９の端面を真空吸着して基
準部材８上に固定する。等の様々な固定手段で行う。In the reference member attaching step shown in FIG. 2B, after the ball flattening step described later, the flat surface formed on the ball end surface is bonded to the reference member 8 with an adhesive, for example, a hot-dip made by Nitto Denko Corporation. A flat surface is formed by applying a fixing means such as a peeling tape “ELEP HOLDER pressure-sensitive dicing tape, SPV-224”, or the surface of a ball electrode 9 described later is buried with resin to form a flat surface, and the flat surface is bonded to the reference member 8. A part of the end face of the ball electrode 9 is buried in a material that changes state into a solid and a liquid depending on the temperature, which will be described later, and is fixed on the reference member 8 in a solid state. . Further, the end face of the ball electrode 9 is fixed by vacuum suction on the reference member 8. And other various fixing means.

【００３８】図２（ｃ）はタイシング工程で、前述の
Ｘ、Ｙ方向のカットライン２に沿って、ダイシングソ
ー、例えば、ディスコ製のダイシング機「ＤＦＤ−６４
０」、使用ブレード「ＮＢＣ−ＺＢ１０９０Ｓ３、０．
１ｍｍ幅」等を使用した切削手段で単個に切削、分割し
た後、溶解液、例えば、日化精工（株）製のワックス
「スカイワックス４１５」等を使用して基準部材８より
剥離する。以上の工程により単個のフリップチップＢＧ
Ａ１０が完成される。FIG. 2C shows a dicing process along a cutting line 2 in the X and Y directions described above, for example, a dicing machine "DFD-64" manufactured by Disco.
0 ", the blade used" NBC-ZB1090S3, 0.
After cutting and dividing into single pieces by a cutting means using “1 mm width” or the like, it is separated from the reference member 8 using a dissolving solution, for example, a wax “Sky Wax 415” manufactured by Nikka Seiko Co., Ltd. Through the above steps, a single flip chip BG
A10 is completed.

【００３９】図３（ａ）、（ｂ）は共に前述したボール
電極９の端面の平坦化工程を示す。図３（ａ）は、ボー
ル電極９の端面をグラインディング等の切削手段で所定
量切削することにより平坦面９ａを形成するものであ
る。FIGS. 3A and 3B both show the step of flattening the end face of the ball electrode 9 described above. FIG. 3A shows a flat surface 9a formed by cutting the end surface of the ball electrode 9 by a predetermined amount using a cutting means such as grinding.

【００４０】図３（ｂ）は、ボール電極９の端面側を熱
板１１の上に載せて、熱板１１を所定の温度に保持する
ことにより、ボール電極９の端面は一定量融けて平坦面
９ａを形成することができる。FIG. 3B shows a state in which the end face of the ball electrode 9 is placed on the hot plate 11 and the hot plate 11 is maintained at a predetermined temperature, so that the end face of the ball electrode 9 is melted by a certain amount and flattened. The surface 9a can be formed.

【００４１】図４（ａ）は前述した樹脂によりボール電
極９面側の平坦化工程を示す。図に示すように、集合回
路基板１Ａのボール電極９側を上にして、前記集合回路
基板１Ａの外周縁部を囲むように、金属又はプラスチッ
ク部材等よりなる枠部材１２を載せて、前記ボール電極
９が埋没するように樹脂１３を充填して、平坦面１３ａ
を形成するものである。FIG. 4A shows a step of flattening the surface of the ball electrode 9 with the above-mentioned resin. As shown in the drawing, a frame member 12 made of a metal or a plastic member or the like is placed so that the ball electrode 9 side of the collective circuit board 1A faces upward and surrounds the outer peripheral edge of the collective circuit board 1A. A resin 13 is filled so that the electrode 9 is buried, and a flat surface 13a is formed.
Is formed.

【００４２】図４（ｂ）は前述した液体によりボール電
極９面を固定する工程を示す。図に示すように、後述す
る周知のペリティエ素子１４の上に基準部材８を載置
し、基準部材８の上面に液体１５を満たした浴槽１６を
設ける。前記液体１５は、温度変化により可逆的に固体
と液体の状態に変化する特性を持つ材料で、液体の状態
でボール電極９の端面の一部を埋没させて、固体の状態
でボール電極９を基準部材８に固定するものである。FIG. 4B shows a step of fixing the surface of the ball electrode 9 with the liquid described above. As shown in the figure, a reference member 8 is placed on a well-known perrier device 14 described later, and a bath 16 filled with a liquid 15 is provided on the upper surface of the reference member 8. The liquid 15 is a material having a characteristic of reversibly changing between a solid state and a liquid state by a change in temperature. The liquid 15 is buried in a part of the end face of the ball electrode 9 in a liquid state, and the ball electrode 9 is It is fixed to the reference member 8.

【００４３】前記ペリティエ素子は、一般にある方向に
電流を流すと冷却し、その反対方向に電流を流すと発熱
する素子で、接着剤に水を使い、冷却し、水を凍らし
て、ボール接着し、ダイシング後に発熱させ水を溶かし
て剥離するものである。The above-mentioned perilier element is generally an element that cools when a current is applied in a certain direction and generates heat when an electric current is applied in the opposite direction. It uses water as an adhesive, cools, freezes the water, and bonds the ball. Then, after dicing, heat is generated to dissolve water and peel off.

【００４４】前記水の代わりに、ワックス等、例えば、
市販のアピエゾンを使用して、高温で溶かし、低温（室
温）で固体化して接着させる手段もある。Instead of the water, wax or the like, for example,
There is also a means of using a commercially available apiezone to melt at a high temperature and solidify at a low temperature (room temperature) to adhere.

【００４５】前記樹脂による平坦面形成工程は、スクリ
ーン印刷により、ボール電極９を樹脂で埋没してもよ
い。例えば、アサヒ化研の商品名「Ｔ−３１」のメタル
マスクを使用してスクリーン印刷し、略１３０°Ｃ程度
で硬化させて平坦面を形成し、基準部材８に真空吸着さ
せてもよい。切削後は回路基板面からメタルマスクを容
易に剥離することができる。In the step of forming a flat surface with the resin, the ball electrode 9 may be buried in the resin by screen printing. For example, screen printing may be performed using a metal mask “T-31” (trade name of Asahi Kaken), cured at about 130 ° C. to form a flat surface, and vacuum-adsorbed to the reference member 8. After the cutting, the metal mask can be easily peeled off from the circuit board surface.

【００４６】また、樹脂による平坦面形成工程は、前述
したようにボール電極９の間に樹脂を流し込んでもよ
い。In the step of forming a flat surface with a resin, the resin may be poured between the ball electrodes 9 as described above.

【００４７】前記基準部材８への固定工程は、紫外線反
応型樹脂で固着してもよい。ＵＶテープ、例えば、日東
電工（株）製のＵＶテープ「ＵＥ−２０９１Ｊ」等を使
用する。前記ＵＶテープは両面接着剤のように使用して
接着する。剥がす前にＵＶを照射すると接着力が極端に
低下するので剥がすのが容易である。In the step of fixing to the reference member 8, the fixing may be performed with an ultraviolet-reactive resin. A UV tape, for example, a UV tape “UE-2091J” manufactured by Nitto Denko Corporation is used. The UV tape is adhered using a double-sided adhesive. If UV irradiation is performed before the peeling, the adhesive force is extremely reduced, so that the peeling is easy.

【００４８】また、基準部材８への固定工程は、熱反応
型樹脂で固着してもよい。Further, in the fixing step to the reference member 8, it may be fixed by a heat-reactive resin.

【００４９】また、基準部材８への固定工程は、溶剤反
応型樹脂で固着してもよい。Further, in the step of fixing to the reference member 8, it may be fixed by a solvent-reactive resin.

【００５０】また、基準部材８への固定工程は、前述し
たようにボール電極９の端面を真空吸着孔を有するチャ
ックテーブル等で真空吸着してもよい。真空吸着しなが
ら、前述のタイシング装置にセットして、直交するＸ、
Ｙ方向にカットライン２に沿ってメタルブレードで切
断、分離する。In the step of fixing the ball electrode 9 to the reference member 8, as described above, the end face of the ball electrode 9 may be vacuum-adsorbed by a chuck table or the like having a vacuum suction hole. While vacuum suction, set on the above-mentioned tying device,
It is cut and separated by a metal blade along the cut line 2 in the Y direction.

【００５１】図５は、電解メッキ法によって、回路基板
上に複数個分のＣＳＰ用等の回路パターンを形成した集
合回路基板１Ａを示す平面図である。この集合回路基板
１Ａは、Ｘ方向に延在する２本の共通電極１４を有し、
更に、共通電極１４に接続してＹ方向に延在する複数本
の共通電極１４ａを有しいる。Ｙ方向に延在する複数本
の共通電極１４ａは、それぞれ両側にＣＳＰ用の製品の
回路パターン１４ｃに連なる枝状の配線パターン１４ｂ
が形成されている。FIG. 5 is a plan view showing an integrated circuit board 1A in which a plurality of circuit patterns for CSP and the like are formed on a circuit board by electrolytic plating. The integrated circuit board 1A has two common electrodes 14 extending in the X direction,
Further, it has a plurality of common electrodes 14a connected to the common electrode 14 and extending in the Y direction. A plurality of common electrodes 14a extending in the Y direction are provided on each side with a branch-like wiring pattern 14b connected to a circuit pattern 14c of a CSP product.
Are formed.

【００５２】この集合回路基板１Ａに対しては、前述の
実施の形態で説明した工程と同様な手順でＩＣチップの
実装、封止、突起電極付けを行い、そして基準部材に突
起電極を固定する。ここで切削工程を行う場合、電解メ
ッキ法による回路基板では、共通電極から個々の配線パ
ターンを切り離すように切削する必要があるので、図に
示すＸ方向の切削手順としては、通常はＡ、Ｂ、Ｃ・・
・Ｊ、Ｋと行うところだが、Ｙ方向の共通電極１４ｂ部
分の切削間隔（Ｂ−Ｃ、Ｅ−Ｆ・・・Ｉ−Ｊの間隔）は
他の部分の間隔に比較して狭く、連続して切削すると下
面側での基準部材に対する固着力が弱いので、切削中に
回路基板が変形したり、切削ラインがずれたりする等の
問題があった。On this collective circuit board 1A, mounting, sealing, and attaching the protruding electrodes are performed by the same procedure as that described in the above embodiment, and the protruding electrodes are fixed to the reference member. . In the case where the cutting step is performed, in the case of a circuit board formed by the electrolytic plating method, it is necessary to perform cutting so as to separate the individual wiring patterns from the common electrode. , C ...
-Although it is a place to perform J and K, the cutting interval (BC, EF ... IJ interval) of the common electrode 14b portion in the Y direction is narrower and continuous than the interval of the other portions. When cutting is performed, the fixing force to the reference member on the lower surface side is weak, so that there are problems such as deformation of the circuit board during cutting and displacement of the cutting line.

【００５３】そこで、本実施の形態によれば、Ｘ方向の
切削の手順をＡ、Ｂ、Ｄ、Ｅ、Ｇ、Ｈ、Ｉ、Ｋ、Ｃ、
Ｆ、Ｊと行うことにより、切削間隔の狭い共通電極部分
を連続切削しないので、回路基板に変形、切削ラインの
ずれ等の問題が生ぜずに切削できるものである。Therefore, according to the present embodiment, the procedure of cutting in the X direction is A, B, D, E, G, H, I, K, C,
By performing steps F and J, the common electrode portion with a small cutting interval is not continuously cut, so that cutting can be performed without causing problems such as deformation of the circuit board and displacement of the cutting line.

【００５４】[0054]

【発明の効果】以上説明したように、本発明の半導体パ
ッケージの製造方法によれば、前記集合回路基板の上面
側に複数個分配列して回路基板にＩＣチップを実装し、
封止樹脂でサイドモールドして、下面側の外部接続用電
極に突起電極を形成後、突起電極を基準部材に固定した
後、切削して単個の半導体パッケージを製造することに
より、小型携帯機器等に搭載する信頼性及び生産性の優
れた半導体パッケージの製造方法を提供することが可能
である。As described above, according to the semiconductor package manufacturing method of the present invention, a plurality of IC chips are arranged on the circuit board by arranging a plurality of IC chips on the upper surface side of the collective circuit board.
Small-sized portable equipment by side-molding with sealing resin, forming a protruding electrode on the external connection electrode on the lower surface side, fixing the protruding electrode to the reference member, and cutting to produce a single semiconductor package Thus, it is possible to provide a method of manufacturing a semiconductor package having excellent reliability and productivity mounted on a semiconductor device.

【図面の簡単な説明】[Brief description of the drawings]

【図１】本発明の実施の形態に係わる半導体パッケージ
の製造工程で、回路基板形成工程、ＩＣ実装工程、樹脂
封止工程を示す説明図である。FIG. 1 is an explanatory view showing a circuit board forming step, an IC mounting step, and a resin sealing step in a manufacturing process of a semiconductor package according to an embodiment of the present invention.

【図２】図１の製造工程後のボール付け工程、基準部材
張り付け工程、ダイシング工程を示す説明図である。FIG. 2 is an explanatory view showing a ball attaching step, a reference member attaching step, and a dicing step after the manufacturing step of FIG. 1;

【図３】ボール電極のボール平坦化工程を示す断面図で
ある。図である。FIG. 3 is a cross-sectional view illustrating a ball flattening step of the ball electrode. FIG.

【図４】樹脂によるボール面平坦化工程工程及び液体に
よるボール面固定工程を示す断面図である。FIG. 4 is a cross-sectional view showing a ball surface flattening step using a resin and a ball surface fixing step using a liquid.

【図５】電解メッキ法によって回路基板上に複数個の回
路パターンを形成した集合回路基板を示す平面図であ
る。FIG. 5 is a plan view showing a collective circuit board in which a plurality of circuit patterns are formed on a circuit board by an electrolytic plating method.

【図６】従来の短冊状のＢＧＡの平面図である。FIG. 6 is a plan view of a conventional strip-shaped BGA.

【図７】従来のＢＧＡの製造工程で、回路基板形成工
程、ＩＣ実装工程、樹脂封止工程を示す説明図である。FIG. 7 is an explanatory view showing a circuit board forming step, an IC mounting step, and a resin sealing step in a conventional BGA manufacturing process.

【図８】従来のＢＧＡの製造工程で、図６の製造工程後
の基準部材張り付け工程、ダイシング工程、ボール付け
工程を示す説明図である。FIG. 8 is an explanatory view showing a reference member attaching step, a dicing step, and a ball attaching step after the manufacturing step of FIG. 6 in a conventional BGA manufacturing step.

【符号の説明】[Explanation of symbols]

１ 回路基板 １Ａ 集合回路基板 ２ カットライン ３ ＩＣ接続用電極 ４ 外部接続用電極 ５ 半田ボール ６ ＩＣチップ ７ 封止樹脂 ８ 基準部材 ９ ボール電極（突起電極） ９ａ 平坦面 １０ フリップチップＢＧＡ １１ 熱板 １２ 枠部材 １３ 樹脂 １４ ペリティエ素子 １５ 液体 DESCRIPTION OF SYMBOLS 1 Circuit board 1A Assembly circuit board 2 Cut line 3 IC connection electrode 4 External connection electrode 5 Solder ball 6 IC chip 7 Sealing resin 8 Reference member 9 Ball electrode (projection electrode) 9a Flat surface 10 Flip chip BGA 11 Hot plate 12 Frame member 13 Resin 14 Peritier element 15 Liquid

───────────────────────────────────────────────────── フロントページの続き (72)発明者 西方 進一 東京都田無市本町６丁目１番12号 シチズ ン時計株式会社田無製造所内 (72)発明者 小村 敦 埼玉県所沢市大字下富字武野840番地 シ チズン時計株式会社技術研究所内 ──────────────────────────────────────────────────続 き Continuing on the front page (72) Inventor Shinichi Nishikata 6-11-12 Honcho, Tanashi-shi, Tokyo Citizen Watch Co., Ltd. Tanashi Factory (72) Inventor Atsushi Komura 840 Takeno Shimotomi, Tomozawa, Tokorozawa-shi, Saitama Address Citizen Watch Co., Ltd.

Claims (15)

【特許請求の範囲】[Claims] 【請求項１】 ＩＣチップを実装した半導体パッケージ
の製造方法において、前記ＩＣチップ実装用のボンディ
ングパターンと外部接続用電極を形成するための電極パ
ターンとを集合回路基板面に複数個分配列して形成する
回路基板形成工程と、前記ボンディングパターンと前記
ＩＣチップを電気的接続するＩＣチップ実装工程と、該
ＩＣチップを樹脂封止する封止工程と、前記外部接続用
電極に突起電極を形成する電極形成工程とによりパッケ
ージ集合体を形成し、該パッケージ集合体の突起電極を
基準部材に固定する保持工程と、保持されたパッケージ
集合体の回路基板を切削して単個の完成半導体パッケー
ジを形成する切削工程とからなることを特徴とする半導
体パッケージの製造方法。1. A method of manufacturing a semiconductor package on which an IC chip is mounted, wherein a plurality of bonding patterns for mounting the IC chip and electrode patterns for forming external connection electrodes are arranged on the surface of the collective circuit board. A circuit board forming step of forming, an IC chip mounting step of electrically connecting the bonding pattern to the IC chip, a sealing step of resin-sealing the IC chip, and forming a protruding electrode on the external connection electrode A package assembly is formed by the electrode forming process, a holding process of fixing the projecting electrodes of the package assembly to the reference member, and a circuit board of the held package assembly is cut to form a single completed semiconductor package A method of manufacturing a semiconductor package, comprising: 【請求項２】 前記パッケージ集合体保持工程は、突起
電極の端面を平坦化する平坦化工程と、該平坦化された
突起電極を基準部材に固着する固定工程とからなること
を特徴とする請求項１記載の半導体パッケージの製造方
法。2. The package assembly holding step includes a flattening step of flattening an end surface of the bump electrode, and a fixing step of fixing the flattened bump electrode to a reference member. Item 2. The method for manufacturing a semiconductor package according to Item 1. 【請求項３】 前記平坦化工程は、突起電極の端面を切
削して平坦化することを特徴とする請求項２記載の半導
体パッケージの製造方法。3. The semiconductor package manufacturing method according to claim 2, wherein in the flattening step, an end face of the protruding electrode is cut and flattened. 【請求項４】 前記平坦化工程は、突起電極の端面を加
熱して平坦化することを特徴とする請求項２記載の半導
体パッケージの製造方法。4. The method according to claim 2, wherein the flattening step heats and flattens an end face of the bump electrode. 【請求項５】 前記突起電極を基準部材に固定する保持
工程は、接着剤で固着することを特徴とする請求項１又
は２記載の半導体パッケージの製造方法。5. The method of manufacturing a semiconductor package according to claim 1, wherein the holding step of fixing the protruding electrode to the reference member is performed with an adhesive. 【請求項６】 前記パッケージ集合体保持工程は、突起
電極を樹脂で埋没させ、該樹脂により突起電極側に平坦
面を形成する平坦面形成工程と、該平坦面を基準部材に
固着する固定工程とからなることを特徴とする請求項１
記載の半導体パッケージの製造方法。6. The package assembly holding step includes: a step of forming a flat surface on the side of the protruding electrode with the resin by burying the protruding electrode with a resin; and a step of fixing the flat surface to a reference member. 2. The method according to claim 1, wherein
The manufacturing method of the semiconductor package described in the above. 【請求項７】 前記パッケージ集合体保持工程は、基準
部材上に設けられた、温度変化により可逆的に固体と液
体に状態変化する材料内に、液体の状態で突起電極の端
面の一部を埋没し、固体の状態で基準部材上に固着する
固定工程とからなることを特徴とする請求項１記載の半
導体パッケージの製造方法。7. The package assembly holding step includes, in a material provided on a reference member, which reversibly changes into a solid and a liquid due to a temperature change, a part of the end surface of the projecting electrode in a liquid state. 2. The method for manufacturing a semiconductor package according to claim 1, further comprising a fixing step of burying and fixing the semiconductor package on a reference member in a solid state. 【請求項８】 前記樹脂による平坦面形成工程は、スク
リーン印刷による樹脂で埋没したことを特徴とする請求
項６記載の半導体パッケージの製造方法。8. The method of manufacturing a semiconductor package according to claim 6, wherein the step of forming the flat surface with the resin is buried with a resin by screen printing. 【請求項９】 前記樹脂による平坦面形成工程は、突起
電極間に樹脂を樹脂を流し込むことにより、樹脂で埋没
したことを特徴とする請求項６記載の半導体パッケージ
の製造方法。9. The method of manufacturing a semiconductor package according to claim 6, wherein in the step of forming the flat surface with the resin, the resin is buried in the resin by pouring the resin between the projecting electrodes. 【請求項１０】 前記固定工程は、紫外線反応型樹脂で
固着したことを特徴とする請求項５記載の半導体パッケ
ージの製造方法。10. The method of manufacturing a semiconductor package according to claim 5, wherein said fixing step is performed by fixing with an ultraviolet reactive resin. 【請求項１１】 前記固定工程は、熱反応型樹脂で固着
したことを特徴とする請求項５記載の半導体パッケージ
の製造方法。11. The method for manufacturing a semiconductor package according to claim 5, wherein said fixing step is performed by fixing with a heat-reactive resin. 【請求項１２】 前記固定工程は、溶剤反応型樹脂で固
着したことを特徴とする請求項５記載の半導体パッケー
ジの製造方法。12. The method of manufacturing a semiconductor package according to claim 5, wherein said fixing step is performed by fixing with a solvent type resin. 【請求項１３】 前記保持工程は、突起電極の端面を真
空吸着したことを特徴とする請求項１〜４、６、８、９
記載の半導体パッケージの製造方法。13. The holding step, wherein an end face of the protruding electrode is vacuum-adsorbed.
The manufacturing method of the semiconductor package described in the above. 【請求項１４】 前記突起電極は、半田バンプであるこ
とを特徴とする請求項１〜１３記載の半導体パッケージ
の製造方法。14. The method according to claim 1, wherein the protruding electrodes are solder bumps. 【請求項１５】 前記切削工程は、ダイシングソーによ
る切削で行うことを特徴とする請求項１〜１４記載の半
導体パッケージの製造方法。15. The method according to claim 1, wherein the cutting step is performed by cutting with a dicing saw.
JP11922097A 1997-05-09 1997-05-09 Manufacturing method of semiconductor package Expired - Fee Related JP4115553B2 (en)

Priority Applications (9)

Application Number Priority Date Filing Date Title
JP11922097A JP4115553B2 (en) 1997-05-09 1997-05-09 Manufacturing method of semiconductor package
CNB988005794A CN1185702C (en) 1997-05-09 1998-04-24 Process for mfg. semiconductor package and circuit board assembly
EP08167595.1A EP2015359B1 (en) 1997-05-09 1998-04-24 Process for manufacturing a semiconductor package and circuit board substrate
PCT/JP1998/001905 WO1998052220A1 (en) 1997-05-09 1998-04-24 Process for manufacturing semiconductor package and circuit board assembly
EP98917679.7A EP0932198B1 (en) 1997-05-09 1998-04-24 Process for manufacturing semiconductor package and circuit board assembly
KR1019997000071A KR100568571B1 (en) 1997-05-09 1998-04-24 Process for manufacturing a semiconductor package and circuit board aggregation
US09/194,735 US6365438B1 (en) 1997-05-09 1998-04-24 Process for manufacturing semiconductor package and circuit board assembly
TW087106959A TW395033B (en) 1997-05-09 1998-05-06 Process for manufacturing a semiconductor package and circuit board aggregation
MYPI98002064A MY123937A (en) 1997-05-09 1998-05-07 Process for manufacturing semiconductor package and circuit board assembly

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP11922097A JP4115553B2 (en) 1997-05-09 1997-05-09 Manufacturing method of semiconductor package

Publications (2)

Publication Number Publication Date
JPH10308473A true JPH10308473A (en) 1998-11-17
JP4115553B2 JP4115553B2 (en) 2008-07-09

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Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP1003213A3 (en) * 1998-11-18 2001-01-17 Sanyo Electric Co., Ltd. Method of fabricating resin-sealed semiconductor devices
US6544814B1 (en) 1999-07-27 2003-04-08 Mitsubishi Denki Kabushiki Kaisha Method of manufacturing a packaged semiconductor device, and a semiconductor device manufactured thereby

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP1003213A3 (en) * 1998-11-18 2001-01-17 Sanyo Electric Co., Ltd. Method of fabricating resin-sealed semiconductor devices
US6326232B1 (en) 1998-11-18 2001-12-04 Sanyo Electric Co., Ltd. Method of fabricating semiconductor device
US6784523B2 (en) 1998-11-18 2004-08-31 Sanyo Electric Co., Ltd. Method of fabricating semiconductor device
EP2234147A3 (en) * 1998-11-18 2014-05-21 Sanyo Electric Co., Ltd. Method of fabricating resin-sealed semiconductor devices
US6544814B1 (en) 1999-07-27 2003-04-08 Mitsubishi Denki Kabushiki Kaisha Method of manufacturing a packaged semiconductor device, and a semiconductor device manufactured thereby

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